diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2013-02-15 13:52:28 -0800 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-21 22:57:11 +0100 |
commit | 8584b223fe1a0c9da9a94e28b135cfc7414601dc (patch) | |
tree | 9758ff81667e1114ab5ffe191622a918f4be4090 /src/southbridge/intel/lynxpoint/pch.h | |
parent | 738af675d1b29847112f32b3fb2ac2524bb7c4ca (diff) | |
download | coreboot-8584b223fe1a0c9da9a94e28b135cfc7414601dc.tar.xz |
LynxPoint: Move RCBA helper function to its own file
So it can get used in both romstage and ramstage.
Change-Id: Ief9eaafdd91df2a7b668de1a9b83aea3af3ff894
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2802
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r-- | src/southbridge/intel/lynxpoint/pch.h | 49 |
1 files changed, 25 insertions, 24 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6f17d38124..563730eae6 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -83,30 +83,6 @@ void intel_pch_finalize_smm(void); #endif -#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> -#include <arch/acpi.h> -#include "chip.h" -int pch_silicon_revision(void); -int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); -void pch_enable(device_t dev); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG -void pch_log_state(void); -#endif -void acpi_create_intel_hpet(acpi_hpet_t * hpet); - -/* These helpers are for performing SMM relocation. */ -void southbridge_smm_init(void); -void southbridge_trigger_smi(void); -void southbridge_clear_smi_status(void); -#else -void enable_smbus(void); -void enable_usb_bar(void); -int smbus_read_byte(unsigned device, unsigned address); -int early_spi_read(u32 offset, u32 size, u8 *buffer); /* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 @@ -147,6 +123,31 @@ struct rcba_config_instruction u32 or_value; }; +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) +void pch_config_rcba(const struct rcba_config_instruction *rcba_config); +#if !defined(__PRE_RAM__) && !defined(__SMM__) +#include <device/device.h> +#include <arch/acpi.h> +#include "chip.h" +int pch_silicon_revision(void); +int pch_silicon_type(void); +int pch_silicon_supported(int type, int rev); +void pch_enable(device_t dev); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); +#if CONFIG_ELOG +void pch_log_state(void); +#endif +void acpi_create_intel_hpet(acpi_hpet_t * hpet); + +/* These helpers are for performing SMM relocation. */ +void southbridge_smm_init(void); +void southbridge_trigger_smi(void); +void southbridge_clear_smi_status(void); +#else +void enable_smbus(void); +void enable_usb_bar(void); +int smbus_read_byte(unsigned device, unsigned address); +int early_spi_read(u32 offset, u32 size, u8 *buffer); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); #endif |