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authorShawn Nematbakhsh <shawnn@chromium.org>2013-08-13 10:45:21 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 12:03:00 +0100
commit287522749ececda35b52dc9b9e8e704e305ec888 (patch)
tree9bf72bb1d0f2d14d25f09d4925b58790c25c80f9 /src/southbridge/intel/lynxpoint/pch.h
parent190688c65f7c128f2dace3b600d1c0f2e56723ee (diff)
downloadcoreboot-287522749ececda35b52dc9b9e8e704e305ec888.tar.xz
lynxpoint: Add configuration option for SATA gen3 DTLE registers
Allow DTLE DATA / EDGE registers to be configured in board-specific devicetree. Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65716 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4475 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pch.h')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 60f81ee707..32c7d9bd01 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -347,6 +347,14 @@ int early_pch_init(const void *gpio_map,
/* SATA IOBP Registers */
#define SATA_IOBP_SP0G3IR 0xea000151
#define SATA_IOBP_SP1G3IR 0xea000051
+#define SATA_IOBP_SP0DTLE_DATA 0xea002550
+#define SATA_IOBP_SP0DTLE_EDGE 0xea002554
+#define SATA_IOBP_SP1DTLE_DATA 0xea002750
+#define SATA_IOBP_SP1DTLE_EDGE 0xea002754
+
+#define SATA_DTLE_MASK 0xF
+#define SATA_DTLE_DATA_SHIFT 24
+#define SATA_DTLE_EDGE_SHIFT 16
/* USB Registers */
#define EHCI_PWR_CNTL_STS 0x54