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authorPatrick Rudolph <siro@das-labor.org>2016-02-06 18:07:59 +0100
committerMartin Roth <martinroth@google.com>2016-02-23 00:28:06 +0100
commit273a8dca1f7896c73b812ecc2c6cd2572ac51d6a (patch)
treea086a9e33bcef9c6490c6cc706a5aef79651f3b5 /src/southbridge/intel/lynxpoint/pcie.c
parent9a4881a783fa1edc730dc484bb2c293d92e45823 (diff)
downloadcoreboot-273a8dca1f7896c73b812ecc2c6cd2572ac51d6a.tar.xz
southbridge/intel/lynxpoint: Use common gpio.c
Use shared gpio code from common folder, except for INTEL_LYNXPOINT_LP, which has it's own gpio code. Needs test on real hardware ! Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13615 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pcie.c')
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 41e8890b30..17858afdcb 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -20,6 +20,7 @@
#include <device/pciexp.h>
#include <device/pci_ids.h>
#include "pch.h"
+#include <southbridge/intel/common/gpio.h>
static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or);
static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or);