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| author | Ryan Salsamendi <rsalsamendi@hotmail.com> | 2017-07-04 13:14:16 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-10 18:15:11 +0000 |
| commit | 3f2fe18965fc5404e4d095a25dcb1be48e4040a5 (patch) | |
| tree | f17cc962dad56d84ff9eb481564406e8fcced61d /src/southbridge/intel/lynxpoint/pcie.c | |
| parent | 2fdf895867bc258690943475f0d2e8fc7daa6ee5 (diff) | |
| download | coreboot-3f2fe18965fc5404e4d095a25dcb1be48e4040a5.tar.xz | |
southbridge/intel/lynxpoint: Fix undefined behavior
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/pcie.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pcie.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 3d01cd6660..006bec2200 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -193,6 +193,8 @@ static void pcie_enable_clock_gating(void) rp = root_port_number(dev); if (!dev->enabled) { + static const uint32_t high_bit = (1UL << 31); + /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) pci_update_config8(dev, 0xe1, 0xc3, 0x3c); @@ -214,7 +216,7 @@ static void pcie_enable_clock_gating(void) } pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config32(dev, 0x420, ~high_bit, high_bit); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) |