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| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/southbridge/intel/lynxpoint/serialio.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
| download | coreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.xz | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel/lynxpoint/serialio.c')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/serialio.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 75edf5c9db..398895a2e9 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -32,9 +32,9 @@ /* Enable clock in PCI mode */ static void serialio_enable_clock(struct resource *bar0) { - u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK); + u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0)); reg32 |= SIO_REG_PPR_CLOCK_EN; - write32(bar0->base + SIO_REG_PPR_CLOCK, reg32); + write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32); } /* Put Serial IO D21:F0-F6 device into desired mode. */ @@ -85,22 +85,22 @@ static void serialio_d21_ltr(struct resource *bar0) u32 reg; /* 1. Program BAR0 + 808h[2] = 0b */ - reg = read32(bar0->base + SIO_REG_PPR_GEN); + reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; - write32(bar0->base + SIO_REG_PPR_GEN, reg); + write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg); /* 2. Program BAR0 + 804h[1:0] = 00b */ - reg = read32(bar0->base + SIO_REG_PPR_RST); + reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); reg &= ~SIO_REG_PPR_RST_ASSERT; - write32(bar0->base + SIO_REG_PPR_RST, reg); + write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); /* 3. Program BAR0 + 804h[1:0] = 11b */ - reg = read32(bar0->base + SIO_REG_PPR_RST); + reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); reg |= SIO_REG_PPR_RST_ASSERT; - write32(bar0->base + SIO_REG_PPR_RST, reg); + write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); /* 4. Program BAR0 + 814h[31:0] = 00000000h */ - write32(bar0->base + SIO_REG_AUTO_LTR, 0); + write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0); } /* Enable LTR Auto Mode for D23:F0. */ @@ -109,26 +109,26 @@ static void serialio_d23_ltr(struct resource *bar0) u32 reg; /* Program BAR0 + 1008h[2] = 1b */ - reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN); + reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0)); reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; - write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg); + write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg); /* Program BAR0 + 1010h = 0x00000000 */ - write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0); + write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0); /* Program BAR0 + 3Ch[30] = 1b */ - reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12); + reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0)); reg |= SIO_REG_SDIO_PPR_CMD12_B30; - write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg); + write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg); } /* Select I2C voltage of 1.8V or 3.3V. */ static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) { - u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN); + u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); - write32(bar0->base + SIO_REG_PPR_GEN, reg32); + write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32); } /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ |