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authorDuncan Laurie <dlaurie@chromium.org>2012-12-12 09:22:34 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 06:36:21 +0100
commit138f2cede491b65cfd8c73b9185a2dc7ee10b8b3 (patch)
treef429c33a4286531502f237403fa4d77d5d74389c /src/southbridge/intel/lynxpoint/smihandler.c
parent89f79a019fd049f26ed7bf40618ff960bd9e095e (diff)
downloadcoreboot-138f2cede491b65cfd8c73b9185a2dc7ee10b8b3.tar.xz
haswell: remove GPIO60 memory reset gate on S3 transition
This is no longer tied to a GPIO but has a proper chipset pin. Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2643 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint/smihandler.c')
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c38
1 files changed, 0 insertions, 38 deletions
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index d31e350b76..7c982d129a 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -290,41 +290,6 @@ static void busmaster_disable_on_bus(int bus)
}
}
-/*
- * Drive GPIO 60 low to gate memory reset in S3.
- *
- * Intel reference designs all use GPIO 60 but it is
- * not a requirement and boards could use a different pin.
- */
-static void southbridge_gate_memory_reset(void)
-{
- u32 reg32;
- u16 gpiobase;
-
- gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
- if (!gpiobase)
- return;
-
- /* Make sure it is set as GPIO */
- reg32 = inl(gpiobase + GPIO_USE_SEL2);
- if (!(reg32 & (1 << 28))) {
- reg32 |= (1 << 28);
- outl(reg32, gpiobase + GPIO_USE_SEL2);
- }
-
- /* Make sure it is set as output */
- reg32 = inl(gpiobase + GP_IO_SEL2);
- if (reg32 & (1 << 28)) {
- reg32 &= ~(1 << 28);
- outl(reg32, gpiobase + GP_IO_SEL2);
- }
-
- /* Drive the output low */
- reg32 = inl(gpiobase + GP_LVL2);
- reg32 &= ~(1 << 28);
- outl(reg32, gpiobase + GP_LVL2);
-}
-
static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
{
u8 reg8;
@@ -372,9 +337,6 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat
case 5:
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
- /* Gate memory reset */
- southbridge_gate_memory_reset();
-
/* Invalidate the cache before going to S3 */
wbinvd();
break;