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authorAngel Pons <th3fanbus@gmail.com>2020-07-07 22:11:13 +0200
committerMichael Niewöhner <c0d3z3r0@review.coreboot.org>2020-07-09 21:20:53 +0000
commit0a65b738d590bb1ef8b51120681125ca40b1f6a9 (patch)
tree6e18ad1f532556016899bfffdb1caf486eac4729 /src/southbridge/intel/lynxpoint
parent5ac928dd145aa8e5526af61ca525765b02919070 (diff)
downloadcoreboot-0a65b738d590bb1ef8b51120681125ca40b1f6a9.tar.xz
sb/intel/lynxpoint/pcie.c: Drop dead code
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43217 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c11
1 files changed, 0 insertions, 11 deletions
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index d957e8d3c8..883dfc781b 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -670,17 +670,6 @@ static void pci_init(struct device *dev)
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
-#ifdef EVEN_MORE_DEBUG
- reg32 = pci_read_config32(dev, 0x20);
- printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x24);
- printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x28);
- printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
- reg32 = pci_read_config32(dev, 0x2c);
- printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
-#endif
-
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, 0x06);
pci_write_config16(dev, 0x06, reg16);