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authorPrabal Saha <coolstarorganization@gmail.com>2016-06-18 20:47:21 -0700
committerMartin Roth <martinroth@google.com>2016-08-02 00:47:26 +0200
commit0f2025da0fd4dce6b951b4c4b97c9370ca7d66db (patch)
treeea6a90f6d4387b86c984bb0f16ea2e10f5c2446b /src/southbridge/intel/lynxpoint
parent6e8233a60b475ff56bfe672293f081653e552510 (diff)
downloadcoreboot-0f2025da0fd4dce6b951b4c4b97c9370ca7d66db.tar.xz
intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano
Without this patch, eDP output is non-functional pre-graphics driver regardless of payload (SeaBIOS, Tianocore) or video init method (VBIOS, GOP driver) and once the standard Windows Intel HD graphics driver is loaded. Test: Boot Windows on peppy and auron_paine, install Intel HD Graphics driver, observe functional eDP output with full video acceleration. Debugging method: adjust location of call to run VBIOS within coreboot, observed that eDP output functional if the VBIOS is run before the power optimizer lines, broken if run afterwards. Change-Id: I6d8252e3de396887c84533e355f41693b9ea7514 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/15261 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig9
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
2 files changed, 11 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index eea0c01043..7615e69cc3 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -96,4 +96,13 @@ config LOCK_MANAGEMENT_ENGINE
bool
default n
+config LYNXPOINT_POWER_OPTIMIZER
+ bool "Enable Power Optimizer"
+ default y if CHROMEOS
+ help
+ Enable the power optimizer for the High Speed I/O
+ Power Control (HSIOPC). This can break graphics
+ under Windows, but can improve battery life under
+ 'mostly idle' conditions.
+
endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f4c3826aa9..1d20bbbe3b 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -346,6 +346,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x33b4, 0, 0x00007001),
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
+#if IS_ENABLED(CONFIG_LYNXPOINT_POWER_OPTIMIZER)
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
@@ -353,6 +354,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */
RCBA_RMW_REG_32(0x3a80, 0, 0x05145005),
+#endif
RCBA_END_CONFIG
};