summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/lynxpoint
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-12 01:06:23 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-14 16:04:56 +0000
commit30392ae396ad46adbcb0ff187579473f780cbe1e (patch)
tree224a050dae81537563f62bdaf1b68812e6b06e33 /src/southbridge/intel/lynxpoint
parent20cf396c960dcf32e321cc61e31db36e78afaa55 (diff)
downloadcoreboot-30392ae396ad46adbcb0ff187579473f780cbe1e.tar.xz
sb/intel/lynxpoint: Define SerialIO devfns
This reduces differences with Broadwell. Tested with BUILD_TIMELESS=1, Google Panther remains identical. Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h11
-rw-r--r--src/southbridge/intel/lynxpoint/serialio.c16
2 files changed, 19 insertions, 8 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 896454fc08..db3d92af26 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -143,6 +143,17 @@ void mainboard_config_rcba(void);
#define PCH_PCS 0x84
#define PCH_PCS_PS_D3HOT 3
+/* SerialIO */
+#define PCH_DEVFN_SDMA PCI_DEVFN(0x15, 0)
+#define PCH_DEVFN_I2C0 PCI_DEVFN(0x15, 1)
+#define PCH_DEVFN_I2C1 PCI_DEVFN(0x15, 2)
+#define PCH_DEVFN_SPI0 PCI_DEVFN(0x15, 3)
+#define PCH_DEVFN_SPI1 PCI_DEVFN(0x15, 4)
+#define PCH_DEVFN_UART0 PCI_DEVFN(0x15, 5)
+#define PCH_DEVFN_UART1 PCI_DEVFN(0x15, 6)
+
+#define PCH_DEVFN_SDIO PCI_DEVFN(0x17, 0)
+
#define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0)
#define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0)
#define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0)
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 77da5351ad..08f69fbc63 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -151,51 +151,51 @@ static void serialio_init(struct device *dev)
serialio_enable_clock(bar0);
switch (dev->path.pci.devfn) {
- case PCI_DEVFN(21, 0): /* SDMA */
+ case PCH_DEVFN_SDMA: /* SDMA */
sio_index = SIO_ID_SDMA;
serialio_init_once(config->sio_acpi_mode);
serialio_d21_mode(sio_index, SIO_PIN_INTB,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(21, 1): /* I2C0 */
+ case PCH_DEVFN_I2C0: /* I2C0 */
sio_index = SIO_ID_I2C0;
serialio_d21_ltr(bar0);
serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage);
serialio_d21_mode(sio_index, SIO_PIN_INTC,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(21, 2): /* I2C1 */
+ case PCH_DEVFN_I2C1: /* I2C1 */
sio_index = SIO_ID_I2C1;
serialio_d21_ltr(bar0);
serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage);
serialio_d21_mode(sio_index, SIO_PIN_INTC,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(21, 3): /* SPI0 */
+ case PCH_DEVFN_SPI0: /* SPI0 */
sio_index = SIO_ID_SPI0;
serialio_d21_ltr(bar0);
serialio_d21_mode(sio_index, SIO_PIN_INTC,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(21, 4): /* SPI1 */
+ case PCH_DEVFN_SPI1: /* SPI1 */
sio_index = SIO_ID_SPI1;
serialio_d21_ltr(bar0);
serialio_d21_mode(sio_index, SIO_PIN_INTC,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(21, 5): /* UART0 */
+ case PCH_DEVFN_UART0: /* UART0 */
sio_index = SIO_ID_UART0;
serialio_d21_ltr(bar0);
serialio_d21_mode(sio_index, SIO_PIN_INTD,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(21, 6): /* UART1 */
+ case PCH_DEVFN_UART1: /* UART1 */
sio_index = SIO_ID_UART1;
serialio_d21_ltr(bar0);
serialio_d21_mode(sio_index, SIO_PIN_INTD,
config->sio_acpi_mode);
break;
- case PCI_DEVFN(23, 0): /* SDIO */
+ case PCH_DEVFN_SDIO: /* SDIO */
sio_index = SIO_ID_SDIO;
serialio_d23_ltr(bar0);
serialio_d23_mode(config->sio_acpi_mode);