device: Use pcidev_on_root()

Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

6 files changed, 7 insertions, 7 deletions

diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 27a3b2954c..46e803d82f 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -99,7 +99,7 @@ static int sleep_type_s3(void)
 
 void pch_enable_lpc(void)
 {
-	const struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+	const struct device *dev = pcidev_on_root(0x1f, 0);
 	const struct southbridge_intel_lynxpoint_config *config = NULL;
 
 	/* Set COM1/COM2 decode range */
diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c
index c575db0693..e16e1be18a 100644
--- a/src/southbridge/intel/lynxpoint/elog.c
+++ b/src/southbridge/intel/lynxpoint/elog.c
@@ -112,7 +112,7 @@ void pch_log_state(void)
 {
 	u16 pm1_sts, gen_pmcon_3, tco2_sts;
 	u8 gen_pmcon_2;
-	struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+	struct device *lpc = pcidev_on_root(0x1f, 0);
 	if (!lpc)
 		return;
 
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index 2b07de2735..b6edc8da1f 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -27,7 +27,7 @@ static u16 get_gpio_base(void)
 #if defined(__PRE_RAM__) || defined(__SMM__)
 	return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
 #else
-	return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+	return pci_read_config16(pcidev_on_root(0x1f, 0),
 				 GPIO_BASE) & 0xfffc;
 #endif
 }
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index f0fc22deaf..5b48da0848 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -456,7 +456,7 @@ static void enable_lp_clock_gating(struct device *dev)
 	RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500);
 
 	/* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */
-	if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b)
+	if (pci_read_config8(pcidev_on_root(2, 0), 0x8) >= 0x0b)
 		RCBA32_OR(0x2614, (1 << 26));
 
 	RCBA32_OR(0x900, 0x0000031f);
@@ -775,7 +775,7 @@ static void southbridge_inject_dsdt(struct device *dev)
 
 void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
-	struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+	struct device *dev = pcidev_on_root(0x1f, 0);
 	struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info;
 	u16 pmbase = get_pmbase();
 
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 1fb6d7ad54..b197bbcfc4 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -31,7 +31,7 @@ static pci_devfn_t pch_get_lpc_device(void)
 #else
 static struct device *pch_get_lpc_device(void)
 {
-	return dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+	return pcidev_on_root(0x1f, 0);
 }
 #endif
 
diff --git a/src/southbridge/intel/lynxpoint/watchdog.c b/src/southbridge/intel/lynxpoint/watchdog.c
index 9a867e413a..ec7cb5d0b5 100644
--- a/src/southbridge/intel/lynxpoint/watchdog.c
+++ b/src/southbridge/intel/lynxpoint/watchdog.c
@@ -32,7 +32,7 @@ void watchdog_off(void)
 	unsigned long value, base;
 
 	/* Turn off the ICH7 watchdog. */
-	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+	dev = pcidev_on_root(0x1f, 0);
 
 	/* Enable I/O space. */
 	value = pci_read_config16(dev, 0x04);