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authorMartin Roth <martin@coreboot.org>2019-10-23 21:46:03 -0600
committerPatrick Georgi <pgeorgi@google.com>2019-10-30 11:16:56 +0000
commitff744bf0eee875a03dc98dd6792e3ed0ff4456a0 (patch)
tree691260ffe71abac0bb8e2a5607b0d6f1cfb16028 /src/southbridge/intel/lynxpoint
parent5331a7cff9ebf6f92542eee53e6556a4d5a0dc75 (diff)
downloadcoreboot-ff744bf0eee875a03dc98dd6792e3ed0ff4456a0.tar.xz
src/southbridge: change "unsigned" to "unsigned int"
Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/early_smbus.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lp_gpio.c6
-rw-r--r--src/southbridge/intel/lynxpoint/lp_gpio.h2
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c8
-rw-r--r--src/southbridge/intel/lynxpoint/pch.c2
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h2
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c2
7 files changed, 12 insertions, 12 deletions
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index d3847a5018..f5700401be 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -51,7 +51,7 @@ void enable_smbus(void)
printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index bc8d8a1630..1919d58998 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -127,11 +127,11 @@ int get_gpio(int gpio_num)
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
{
int gpio;
- unsigned bitmask = 1;
- unsigned vector = 0;
+ unsigned int bitmask = 1;
+ unsigned int vector = 0;
while (bitmask &&
((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index fa6d700fd9..8436243f59 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -169,7 +169,7 @@ int get_gpio(int gpio_num);
* get a number comprised of multiple GPIO values. gpio_num_array points to
* the array of gpio pin numbers to scan, terminated by -1.
*/
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
void set_gpio(int gpio_num, int value);
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index b43a1ae39c..59a8666547 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -162,7 +162,7 @@ static inline u32 read_cb(void)
static int mei_wait_for_me_ready(void)
{
struct mei_csr me;
- unsigned try = ME_RETRY;
+ unsigned int try = ME_RETRY;
while (try--) {
read_me_csr(&me);
@@ -202,7 +202,7 @@ static void mei_reset(void)
static int mei_send_packet(struct mei_header *mei, void *req_data)
{
struct mei_csr host;
- unsigned ndata, n;
+ unsigned int ndata, n;
u32 *data;
/* Number of dwords to write */
@@ -306,8 +306,8 @@ static int mei_recv_msg(void *header, int header_bytes,
{
struct mei_header mei_rsp;
struct mei_csr me, host;
- unsigned ndata, n;
- unsigned expected;
+ unsigned int ndata, n;
+ unsigned int expected;
u32 *data;
/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index a57bae311d..dc7b9580d9 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -197,7 +197,7 @@ void pch_disable_devfn(struct device *dev)
#define IOBP_RETRY 1000
static inline int iobp_poll(void)
{
- unsigned try;
+ unsigned int try;
for (try = IOBP_RETRY; try > 0; try--) {
u16 status = RCBA16(IOBPS);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index be4285b1da..d83dd17275 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -177,7 +177,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
void enable_smbus(void);
#if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
#endif
void enable_usb_bar(void);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 1eb8e4bcc4..92dd02e2ed 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -168,7 +168,7 @@ static void root_port_init_config(struct device *dev)
static void pch_pcie_device_set_func(int index, int pci_func)
{
struct device *dev;
- unsigned new_devfn;
+ unsigned int new_devfn;
dev = rpc.ports[index];