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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-19 19:50:51 +0300 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2014-06-21 08:04:52 +0200 |
| commit | c3ed88636a3533b97cef5bcb445cbe61edbfae7f (patch) | |
| tree | 12b51d3abb1876d41a8fd1b2bcf899e316b3d511 /src/southbridge/intel/lynxpoint | |
| parent | 49380b87d114cf4c1bd6f0692f43e89e73f662b8 (diff) | |
| download | coreboot-c3ed88636a3533b97cef5bcb445cbe61edbfae7f.tar.xz | |
intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/elog.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/me_9.x.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/usb_xhci.c | 4 |
4 files changed, 5 insertions, 9 deletions
diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 9ba3a981d3..a2352b387b 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -161,7 +161,7 @@ void pch_log_state(void) /* ACPI Wake */ if (pm1_sts & (1 << 15)) elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_slp_type == 3 ? 3 : 5); + acpi_is_wakeup_s3() ? 3 : 5); /* * Wake sources diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5d1bcdd1c9..6f4063752b 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -499,7 +499,7 @@ static void enable_lp_clock_gating(device_t dev) static void pch_set_acpi_mode(void) { #if CONFIG_HAVE_SMI_HANDLER - if (acpi_slp_type != 3) { + if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); @@ -716,7 +716,7 @@ static void pch_lpc_read_resources(device_t dev) /* Allocate ACPI NVS in CBMEM */ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); - if (acpi_slp_type != 3 && gnvs) + if (!acpi_is_wakeup_s3() && gnvs) memset(gnvs, 0, sizeof(global_nvs_t)); } diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index cb4e97006d..c8ff913824 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -878,13 +878,11 @@ static struct pci_operations pci_ops = { static void intel_me_enable(device_t dev) { -#if CONFIG_HAVE_ACPI_RESUME /* Avoid talking to the device in S3 path */ - if (acpi_slp_type == 3) { + if (acpi_is_wakeup_s3()) { dev->enabled = 0; pch_disable_devfn(dev); } -#endif } static struct device_operations device_ops = { diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 500b57803a..9978c49ff4 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -394,11 +394,9 @@ static void usb_xhci_init(device_t dev) reg32 |= (1 << 31); pci_write_config32(dev, 0x40, reg32); -#if CONFIG_HAVE_ACPI_RESUME /* Enable ports that are disabled before returning to OS */ - if (acpi_slp_type == 3) + if (acpi_is_wakeup_s3()) usb_xhci_enable_ports_usb3(dev); -#endif } static void usb_xhci_set_subsystem(device_t dev, unsigned vendor, |