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authorStefan Reinauer <stepan@coresystems.de>2010-03-17 02:48:24 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-17 02:48:24 +0000
commit68f542cdf82efe257ee4251047a264558dd8645f (patch)
tree087bcdf4ed691b29dee2a97ab8e42b2a1a349d5e /src/southbridge/intel/pxhd
parentb48ba6625b4028a12ddf22ec660922a8dc51113a (diff)
downloadcoreboot-68f542cdf82efe257ee4251047a264558dd8645f.tar.xz
remove more warnings, and fix some boards (watchdog.h)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5239 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/pxhd')
-rw-r--r--src/southbridge/intel/pxhd/pxhd_bridge.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c
index 1a21a9c03e..0766b22e7b 100644
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/pxhd_bridge.c
@@ -64,15 +64,15 @@ static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
}
static void pcix_init(device_t dev)
{
- uint32_t dword;
- uint16_t word;
- uint8_t byte;
- int nmi_option;
-
/* Bridge control ISA enable */
pci_write_config8(dev, 0x3e, 0x07);
+#warning "Please review lots of dead code here."
#if 0
+ int nmi_option;
+ uint32_t dword;
+ uint16_t word;
+ uint8_t byte;
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);