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| author | Zheng Bao <zheng.bao@amd.com> | 2009-06-03 03:15:05 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2009-06-03 03:15:05 +0000 |
| commit | a922b3195b77a3cc82bafad20dd3dfcfd2a61bc0 (patch) | |
| tree | fbe58f136039f1c35ab5fea76fcd7970b63a3a3e /src/southbridge/intel/pxhd | |
| parent | f8318fe8f9af3d92eaf24aea3457a011e5fde134 (diff) | |
| download | coreboot-a922b3195b77a3cc82bafad20dd3dfcfd2a61bc0.tar.xz | |
Modify it based on the RPR 5.7.7. Switching GGSP Configuration By Register Programming.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4331 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/pxhd')
0 files changed, 0 insertions, 0 deletions