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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-10 11:40:54 +0300 |
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committer | Aaron Durbin <adurbin@google.com> | 2013-07-01 17:11:14 +0200 |
commit | 54c586c7e76d9e9ec75ccebaf1555b3fde6114e8 (patch) | |
tree | 64057a00ff889a06753f560138320201b6ccdde9 /src/southbridge/intel/sch/Makefile.inc | |
parent | fb387dfb920f73abb144183b8a41dc917e2e32da (diff) | |
download | coreboot-54c586c7e76d9e9ec75ccebaf1555b3fde6114e8.tar.xz |
usbdebug: Unify Intel southbridge builds
EHCI controller enable is identical on the affected chipsets.
Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3424
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/sch/Makefile.inc')
-rw-r--r-- | src/southbridge/intel/sch/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/sch/Makefile.inc b/src/southbridge/intel/sch/Makefile.inc index 9821fedc33..b321a6c4ca 100644 --- a/src/southbridge/intel/sch/Makefile.inc +++ b/src/southbridge/intel/sch/Makefile.inc @@ -33,7 +33,6 @@ ramstage-y += reset.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-$(CONFIG_USBDEBUG) += usb_debug.c # We don't ship that, but booting without it is bound to fail cbfs-files-$(CONFIG_HAVE_CMC) += cmc.bin |