diff options
author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 07:48:43 +0000 |
---|---|---|
committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 07:48:43 +0000 |
commit | be61a173512ece32de01562995a91fbbf3f5b335 (patch) | |
tree | acf01fc4637bc97ca0e395158254a57ae247a402 /src/southbridge/intel/sch/acpi/usb.asl | |
parent | 312fc96874ff2b3fd1a839b72dd10edb1b8937b8 (diff) | |
download | coreboot-be61a173512ece32de01562995a91fbbf3f5b335.tar.xz |
Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.
Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/sch/acpi/usb.asl')
-rw-r--r-- | src/southbridge/intel/sch/acpi/usb.asl | 217 |
1 files changed, 217 insertions, 0 deletions
diff --git a/src/southbridge/intel/sch/acpi/usb.asl b/src/southbridge/intel/sch/acpi/usb.asl new file mode 100644 index 0000000000..9ae9909a9e --- /dev/null +++ b/src/southbridge/intel/sch/acpi/usb.asl @@ -0,0 +1,217 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Intel i82801G USB support */ + +// USB Controller 0:1d.0 + +Device (USB1) +{ + Name(_ADR, 0x001d0000) + + OperationRegion(U01P, PCI_Config, 0, 256) + Field(U01P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U1WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U1WE) + } Else { + Store (0, U1WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } +} + + +// USB Controller 0:1d.1 + +Device (USB2) +{ + Name(_ADR, 0x001d0001) + + OperationRegion(U02P, PCI_Config, 0, 256) + Field(U02P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U2WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U2WE) + } Else { + Store (0, U2WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// USB Controller 0:1d.2 + +Device (USB3) +{ + Name(_ADR, 0x001d0002) + + OperationRegion(U03P, PCI_Config, 0, 256) + Field(U03P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U3WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U3WE) + } Else { + Store (0, U3WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// USB Controller 0:1d.3 + +Device (USB4) +{ + Name(_ADR, 0x001d0003) + + OperationRegion(U04P, PCI_Config, 0, 256) + Field(U04P, DWordAcc, NoLock, Preserve) + { + Offset(0xc4), + U4WE, 2 // USB Wake Enable + } + + Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake + + Method (_PSW, 1) // Power State Wake method + { + // USB Controller can wake OS from Sleep State + If (Arg0) { + Store (3, U4WE) + } Else { + Store (0, U4WE) + } + } + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + +} + + +// EHCI Controller 0:1d.7 + +Device (EHC1) +{ + Name(_ADR, 0x001d0007) + + Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake + + // Leave USB ports on for to allow Wake from USB + + Method(_S3D,0) // Highest D State in S3 State + { + Return (2) + } + + Method(_S4D,0) // Highest D State in S4 State + { + Return (2) + } + + Device (HUB7) + { + Name (_ADR, 0x00000000) + + // How many are there? + Device (PRT1) { Name (_ADR, 1) } // USB Port 0 + Device (PRT2) { Name (_ADR, 2) } // USB Port 1 + Device (PRT3) { Name (_ADR, 3) } // USB Port 2 + Device (PRT4) { Name (_ADR, 4) } // USB Port 3 + Device (PRT5) { Name (_ADR, 5) } // USB Port 4 + Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + } +} + + |