diff options
| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 07:48:43 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-12-18 07:48:43 +0000 |
| commit | be61a173512ece32de01562995a91fbbf3f5b335 (patch) | |
| tree | acf01fc4637bc97ca0e395158254a57ae247a402 /src/southbridge/intel/sch/chip.h | |
| parent | 312fc96874ff2b3fd1a839b72dd10edb1b8937b8 (diff) | |
| download | coreboot-be61a173512ece32de01562995a91fbbf3f5b335.tar.xz | |
Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.
Compiles, but not boot tested lately.
Many things missing (eg. SMM support, proper ACPI, ...)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/sch/chip.h')
| -rw-r--r-- | src/southbridge/intel/sch/chip.h | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/southbridge/intel/sch/chip.h b/src/southbridge/intel/sch/chip.h new file mode 100644 index 0000000000..116d382768 --- /dev/null +++ b/src/southbridge/intel/sch/chip.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SOUTHBRIDGE_INTEL_SCH_CHIP_H +#define SOUTHBRIDGE_INTEL_SCH_CHIP_H + +struct southbridge_intel_sch_config { + /** + * Interrupt Routing configuration + * If bit7 is 1, the interrupt is disabled. + */ + uint8_t pirqa_routing; + uint8_t pirqb_routing; + uint8_t pirqc_routing; + uint8_t pirqd_routing; + uint8_t pirqe_routing; + uint8_t pirqf_routing; + uint8_t pirqg_routing; + uint8_t pirqh_routing; +}; + +extern struct chip_operations southbridge_intel_sch_ops; + +#endif |