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| author | Idwer Vollering <vidwer@gmail.com> | 2010-12-17 22:34:58 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-12-17 22:34:58 +0000 |
| commit | 312fc96874ff2b3fd1a839b72dd10edb1b8937b8 (patch) | |
| tree | a73f2971e0d8dbf9927f3ab5e933acfc0a5a3d30 /src/southbridge/intel/sch/south.c | |
| parent | 397ff6815f48182e9f05372aefcad55950d2dc36 (diff) | |
| download | coreboot-312fc96874ff2b3fd1a839b72dd10edb1b8937b8.tar.xz | |
inteltool: Model 0xf2x, ICH5, i865 support.
Add support for dumping the MSRs on model_f2x and dumping GPIOs and PM
registers on ICH5. Add ICH5 and i865 to the supported chips list.
Enable the dumping of BAR6 on i865.
Sample output:
Disabling memory access:
$ sudo setpci -s 6.0 0x04.b=0x0
$ sudo ./inteltool -m | head -n 9
Intel CPU: Processor Type: 0, Family f, Model 2, Stepping 7
Intel Northbridge: 8086:2570 (i865)
Intel Southbridge: 8086:24d0 (ICH5)
============= MCHBAR ============
Access to BAR6 is currently disabled, attempting to enable.
Enabled successfully.
BAR6 = 0xfecf0000 (MEM)
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6197 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/sch/south.c')
0 files changed, 0 insertions, 0 deletions