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authorArthur Heymans <arthur@aheymans.xyz>2018-11-27 14:06:21 +0100
committerArthur Heymans <arthur@aheymans.xyz>2018-12-03 10:16:18 +0000
commit009518e79b9b3a7d756243dd6ca1b6789de1430a (patch)
tree1d3096e2a4a780367a6de1798319fada8e0987b7 /src/southbridge/intel
parent66c22508c7ad0147a275b681db9133ff590a14b0 (diff)
downloadcoreboot-009518e79b9b3a7d756243dd6ca1b6789de1430a.tar.xz
nb/intel/gm45: Correctly cache TSEG
Change-Id: I6a8752da9f92b90a2cb2cca5ebf28e2bc5a9c9a8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/29866 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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