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authorArthur Heymans <arthur@aheymans.xyz>2019-06-03 19:36:25 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-06-21 09:18:57 +0000
commit09ccd418f40bad87098e71411e408bf9b5c69881 (patch)
treeeff1d86b10581232f0eaf5876fa39ede25b31101 /src/southbridge/intel
parentfb626dcd78a2a61af728b5479d3babb3ea7e5b36 (diff)
downloadcoreboot-09ccd418f40bad87098e71411e408bf9b5c69881.tar.xz
sb/intel/common: Link SPI code in bootblock
Change-Id: I2874bc37c6bceb2b22115a09ed1501ce917b4623 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 4cf6e6f57e..deab85ff97 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -45,6 +45,7 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c
+bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c
ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI) += spi.c