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authorArthur Heymans <arthur@aheymans.xyz>2019-10-04 13:59:29 +0200
committerArthur Heymans <arthur@aheymans.xyz>2019-10-11 12:21:25 +0000
commit2437fe9dfab8e4056b633a39d51d07aa81ab3c9d (patch)
tree1dd071659a48c99c1e71ddf03b8cdf416da324c2 /src/southbridge/intel
parentcbe5357de02fa9f25ab9c0ca557e3057c701b059 (diff)
downloadcoreboot-2437fe9dfab8e4056b633a39d51d07aa81ab3c9d.tar.xz
sb/intel/i82801gx: Move CIR init to a common place
Some boards with the G41 chipset lacked programming CIR, so this change add that to those boards too. Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801gx/Makefile.inc1
-rw-r--r--src/southbridge/intel/i82801gx/early_cir.c55
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h1
3 files changed, 57 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index 237c2d5f8e..2e9d31a3e8 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -35,5 +35,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
smm-y += smihandler.c
romstage-y += early_smbus.c
+romstage-y += early_cir.c
endif
diff --git a/src/southbridge/intel/i82801gx/early_cir.c b/src/southbridge/intel/i82801gx/early_cir.c
new file mode 100644
index 0000000000..4f08a43b91
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/early_cir.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include "i82801gx.h"
+
+/* Chipset Initialization Registers magic */
+void ich7_setup_cir(void)
+{
+ uint32_t reg32;
+ uint8_t revision = pci_read_config8(PCI_DEV(0, 31, 0), PCI_REVISION_ID);
+ uint16_t pci_id = pci_read_config16(PCI_DEV(0, 31, 0), PCI_DEVICE_ID);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ /* Although bit 6 is set, it is not read back */
+ RCBA32(0x0214) = 0x10030549;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(GCS);
+ reg32 |= (1 << 6);
+ RCBA32(GCS) = reg32;
+ RCBA32_AND_OR(0x3430, ~(3 << 0), 1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ /* Only on mobile variants of revision b0 or later */
+ switch (pci_id) {
+ case 0x27b9:
+ case 0x27bc:
+ case 0x27bd:
+ if (revision >= 2) {
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+ }
+ }
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index d615b403ac..8c85331af9 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -48,6 +48,7 @@ int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,
const u8 *buf);
+void ich7_setup_cir(void);
#endif
#define MAINBOARD_POWER_OFF 0