summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2013-06-19 13:20:37 -0500
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2013-12-02 15:08:22 +0100
commit3fcd356464bd65e8aafa0aae01e7fa6a2f4bc67d (patch)
tree9168980b0da910d163e5c790c2a8189d49d8fe67 /src/southbridge/intel
parentc17aac32f27f6ab18faaabc8a5667bc2a0a10120 (diff)
downloadcoreboot-3fcd356464bd65e8aafa0aae01e7fa6a2f4bc67d.tar.xz
lynxpoint: expose pch_disable_devfn()
The function to disable devices was formerly named pch_hide_devfn(). This routine was doing more than hiding devices. It was disabling them, i.e. turning them off. Therefore, rename it to pch_disable_devfn(). Also, allow external callers to this function. Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59276 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4250 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.c10
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h1
2 files changed, 6 insertions, 5 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index 05462c5e74..f13efb0f7f 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -92,7 +92,7 @@ static void pch_enable_d3hot(device_t dev)
}
/* Set bit in Function Disble register to hide this device */
-static void pch_hide_devfn(device_t dev)
+void pch_disable_devfn(device_t dev)
{
switch (dev->path.pci.devfn) {
case PCI_DEVFN(19, 0): /* Audio DSP */
@@ -432,8 +432,8 @@ static void pch_pcie_enable(device_t dev)
/* Do not claim downstream transactions for PCIe ports */
new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
- /* Hide this device if possible */
- pch_hide_devfn(dev);
+ /* Disable this device if possible */
+ pch_disable_devfn(dev);
} else {
int fn;
@@ -491,8 +491,8 @@ void pch_enable(device_t dev)
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
- /* Hide this device if possible */
- pch_hide_devfn(dev);
+ /* Disable this device if possible */
+ pch_disable_devfn(dev);
} else {
/* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index c46153ca44..7c187054cc 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -162,6 +162,7 @@ void disable_gpe(u32 mask);
#include <arch/acpi.h>
#include "chip.h"
void pch_enable(device_t dev);
+void pch_disable_devfn(device_t dev);
u32 pch_iobp_read(u32 address);
void pch_iobp_write(u32 address, u32 data);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);