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authorPatrick Rudolph <siro@das-labor.org>2018-10-01 19:17:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:35:25 +0000
commit45022ae056cdbf58429b77daf2da176306312801 (patch)
tree4218666e3c14e41232778c4ceff301292b3c61d9 /src/southbridge/intel
parent33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff)
downloadcoreboot-45022ae056cdbf58429b77daf2da176306312801.tar.xz
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/Makefile.inc2
-rw-r--r--src/southbridge/intel/bd82x6x/reset.c28
-rw-r--r--src/southbridge/intel/common/Kconfig5
-rw-r--r--src/southbridge/intel/common/Makefile.inc6
-rw-r--r--src/southbridge/intel/common/reset.c (renamed from src/southbridge/intel/i82801dx/reset.c)9
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/Makefile.inc2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/reset.c29
-rw-r--r--src/southbridge/intel/fsp_i89xx/Kconfig1
-rw-r--r--src/southbridge/intel/fsp_i89xx/Makefile.inc2
-rw-r--r--src/southbridge/intel/fsp_i89xx/reset.c29
-rw-r--r--src/southbridge/intel/fsp_i89xx/romstage.c10
-rw-r--r--src/southbridge/intel/fsp_rangeley/Kconfig1
-rw-r--r--src/southbridge/intel/fsp_rangeley/Makefile.inc3
-rw-r--r--src/southbridge/intel/fsp_rangeley/reset.c30
-rw-r--r--src/southbridge/intel/i82801dx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801dx/Makefile.inc2
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801gx/Makefile.inc1
-rw-r--r--src/southbridge/intel/i82801gx/reset.c37
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig1
-rw-r--r--src/southbridge/intel/i82801ix/Makefile.inc1
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig1
-rw-r--r--src/southbridge/intel/i82801jx/Makefile.inc1
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig1
-rw-r--r--src/southbridge/intel/ibexpeak/Makefile.inc2
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig1
-rw-r--r--src/southbridge/intel/lynxpoint/Makefile.inc5
-rw-r--r--src/southbridge/intel/lynxpoint/reset.c28
30 files changed, 18 insertions, 224 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 16602cf883..20cdeb84e3 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -29,7 +29,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_USBDEBUG_OPTIONS
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index ea8e96c338..d8730dfdd3 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
ramstage-y += me_status.c
-ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
@@ -39,7 +38,6 @@ ramstage-$(CONFIG_ELOG) += elog.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
romstage-y += early_smbus.c me_status.c
-romstage-y += reset.c
romstage-y += early_spi.c early_pch_common.c
romstage-y += early_rcba.c
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
deleted file mode 100644
index 7faadb62df..0000000000
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- outb(0x06, 0xcf9);
-}
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 0f75537247..47a714b323 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -1,5 +1,10 @@
config SOUTHBRIDGE_INTEL_COMMON
def_bool n
+ select SOUTHBRIDGE_INTEL_COMMON_RESET
+
+config SOUTHBRIDGE_INTEL_COMMON_RESET
+ bool
+ select HAVE_CF9_RESET
config SOUTHBRIDGE_INTEL_COMMON_GPIO
def_bool n
diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc
index 961b71bbd8..249d2496ef 100644
--- a/src/southbridge/intel/common/Makefile.inc
+++ b/src/southbridge/intel/common/Makefile.inc
@@ -16,6 +16,12 @@
# CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build.
subdirs-y += firmware
+verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c
+
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y)
romstage-y += pmbase.c
diff --git a/src/southbridge/intel/i82801dx/reset.c b/src/southbridge/intel/common/reset.c
index 1839ad6f9a..5a23afa38e 100644
--- a/src/southbridge/intel/i82801dx/reset.c
+++ b/src/southbridge/intel/common/reset.c
@@ -1,8 +1,6 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2004 Ronald G. Minnich
- *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
@@ -13,11 +11,10 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
+#include <cf9_reset.h>
#include <reset.h>
-void do_hard_reset(void)
+void do_board_reset(void)
{
- /* Try rebooting through port 0xcf9 */
- outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+ system_reset();
}
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig
index cf693f6812..52810ab6c1 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Kconfig
+++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig
@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
index 93253e94ef..07192e2a1b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
@@ -23,7 +23,6 @@ ramstage-y += sata.c
ramstage-y += me.c
ramstage-y += me_8.x.c
ramstage-y += me_status.c
-ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
@@ -37,7 +36,6 @@ romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
smm-$(CONFIG_USBDEBUG) += usb_debug.c
-romstage-y += reset.c
romstage-y += early_spi.c
CPPFLAGS_common += -I$(src)/southbridge/intel/fsp_bd82x6x
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
deleted file mode 100644
index b1468da64b..0000000000
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- outb(0x06, 0xcf9);
-}
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index 9dd62ed742..0bc9586cb2 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
diff --git a/src/southbridge/intel/fsp_i89xx/Makefile.inc b/src/southbridge/intel/fsp_i89xx/Makefile.inc
index d8eb06789f..3d2ab69ee4 100644
--- a/src/southbridge/intel/fsp_i89xx/Makefile.inc
+++ b/src/southbridge/intel/fsp_i89xx/Makefile.inc
@@ -22,7 +22,6 @@ ramstage-y += sata.c
ramstage-y += me.c
ramstage-y += me_8.x.c
ramstage-y += me_status.c
-ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_ELOG) += elog.c
@@ -35,7 +34,6 @@ romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
smm-$(CONFIG_USBDEBUG) += usb_debug.c
-romstage-y += reset.c
romstage-y += early_spi.c
romstage-y += romstage.c
diff --git a/src/southbridge/intel/fsp_i89xx/reset.c b/src/southbridge/intel/fsp_i89xx/reset.c
deleted file mode 100644
index b1468da64b..0000000000
--- a/src/southbridge/intel/fsp_i89xx/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- outb(0x06, 0xcf9);
-}
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index afe00bd6aa..268ea668ba 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -31,7 +31,7 @@
#include <console/usb.h>
#include <halt.h>
#include <program_loading.h>
-#include <reset.h>
+#include <cf9_reset.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <northbridge/intel/fsp_sandybridge/northbridge.h>
#include <northbridge/intel/fsp_sandybridge/raminit.h>
@@ -42,12 +42,6 @@
#include "pch.h"
#include "romstage.h"
-static inline void reset_system(void)
-{
- hard_reset();
- halt();
-}
-
static void pch_enable_lpc(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
@@ -202,7 +196,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
cbmem_was_initted = !cbmem_recovery(0);
if (cbmem_was_initted) {
- reset_system();
+ system_reset();
}
/* Save the HOB pointer in CBMEM to be used in ramstage. */
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index 3cd5861e00..c15c48d445 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 6ab18a7a9d..ace227c92e 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -19,13 +19,12 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_FSP_RANGELEY),y)
ramstage-y += soc.c
ramstage-y += lpc.c
ramstage-y += sata.c
-ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-y += spi.c
ramstage-y += smbus.c
ramstage-y += acpi.c
-romstage-y += early_usb.c early_smbus.c gpio.c reset.c early_spi.c early_init.c
+romstage-y += early_usb.c early_smbus.c gpio.c early_spi.c early_init.c
romstage-y += romstage.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
diff --git a/src/southbridge/intel/fsp_rangeley/reset.c b/src/southbridge/intel/fsp_rangeley/reset.c
deleted file mode 100644
index 10b82ff4e5..0000000000
--- a/src/southbridge/intel/fsp_rangeley/reset.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- hard_reset();
-}
-
-void do_hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/southbridge/intel/i82801dx/Kconfig b/src/southbridge/intel/i82801dx/Kconfig
index 19e890f58b..827f6bb0f6 100644
--- a/src/southbridge/intel/i82801dx/Kconfig
+++ b/src/southbridge/intel/i82801dx/Kconfig
@@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801DX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG
select SOUTHBRIDGE_INTEL_COMMON
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc
index c51488390d..7d87995259 100644
--- a/src/southbridge/intel/i82801dx/Makefile.inc
+++ b/src/southbridge/intel/i82801dx/Makefile.inc
@@ -24,8 +24,6 @@ ramstage-y += lpc.c
ramstage-y += usb.c
ramstage-y += usb2.c
-ramstage-y += reset.c
-
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index fbae6452eb..28d42ffbe9 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -18,7 +18,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select SOUTHBRIDGE_INTEL_COMMON
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index bb68d933b6..0f651e0725 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -30,7 +30,6 @@ ramstage-y += usb_ehci.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
-ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
deleted file mode 100644
index e18f3e8ddc..0000000000
--- a/src/southbridge/intel/i82801gx/reset.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-#if 0
-void do_hard_reset(void)
-{
- /* Try rebooting through port 0xcf9. */
- outb((1 << 2) | (1 << 1), 0xcf9);
-}
-#endif
-
-void do_hard_reset(void)
-{
- outb(0x02, 0xcf9);
- outb(0x06, 0xcf9);
-}
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 0c5aabfc40..571778a020 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -21,7 +21,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select IOAPIC
select HAVE_USBDEBUG
- select HAVE_HARD_RESET
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 32d8221213..3cc7da5ead 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
-ramstage-y += ../i82801gx/reset.c
ramstage-y += ../i82801gx/watchdog.c
ifneq ($(CONFIG_SMM_TSEG),y)
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index cb5b12fcd0..e56d692fb3 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -22,7 +22,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
select IOAPIC
select HAVE_USBDEBUG
- select HAVE_HARD_RESET
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc
index d6a3a7ddf5..1053659d68 100644
--- a/src/southbridge/intel/i82801jx/Makefile.inc
+++ b/src/southbridge/intel/i82801jx/Makefile.inc
@@ -29,7 +29,6 @@ ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
-ramstage-y += ../i82801gx/reset.c
ramstage-y += ../i82801gx/watchdog.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index 5b085b7e1d..fe6526dc88 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -22,7 +22,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_USBDEBUG
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 7714f9578a..906652d565 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -31,7 +31,6 @@ ramstage-y += ../common/pciehp.c
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
ramstage-y += ../bd82x6x/me_status.c
-ramstage-y += ../bd82x6x/reset.c
ramstage-y += ../bd82x6x/watchdog.c
ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
@@ -41,7 +40,6 @@ ramstage-y += smi.c
smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c
romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../common/gpio.c early_thermal.c
-romstage-y += ../bd82x6x/reset.c
romstage-y += ../bd82x6x/early_rcba.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c
romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index dc25b850d8..32485c5c89 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -25,7 +25,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI
select IOAPIC
- select HAVE_HARD_RESET
select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 7ea0d8bccc..db3454691f 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -36,7 +36,6 @@ endif
ramstage-y += rcba.c
ramstage-y += me_status.c
-ramstage-y += reset.c
ramstage-y += watchdog.c
ramstage-y += acpi.c
@@ -47,7 +46,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c pch.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c usb_ehci.c usb_xhci.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
-romstage-y += reset.c early_spi.c rcba.c pmutil.c
+romstage-y += early_spi.c rcba.c pmutil.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
@@ -55,6 +54,4 @@ ramstage-y += lp_gpio.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
endif
-postcar-y += reset.c
-
endif
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
deleted file mode 100644
index 7faadb62df..0000000000
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <reset.h>
-
-void do_soft_reset(void)
-{
- outb(0x04, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- outb(0x06, 0xcf9);
-}