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authorAaron Durbin <adurbin@chromium.org>2013-06-21 13:37:23 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-12-05 20:14:01 +0100
commit550bcca6021f475d4ad7dd2c73d6bc4b5a93f94a (patch)
tree488eaa722dac090f7bc2bfda971b0e12f2ef0cdd /src/southbridge/intel
parentab365af0a05e391d1e20e39e8bfb61c023b0a678 (diff)
downloadcoreboot-550bcca6021f475d4ad7dd2c73d6bc4b5a93f94a.tar.xz
lynxpoint: provide gpio_is_native()
There's a need to determine if a specific gpio pin is is set up to be a native function or not. Implement this. Change-Id: I91d57a549e0f4fddc0b1849e5f74320fc839642c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59589 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4324 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/gpio.c19
-rw-r--r--src/southbridge/intel/lynxpoint/lp_gpio.c7
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h2
3 files changed, 28 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c
index 147a1c013b..c6d6a1522a 100644
--- a/src/southbridge/intel/lynxpoint/gpio.c
+++ b/src/southbridge/intel/lynxpoint/gpio.c
@@ -128,3 +128,22 @@ void set_gpio(int gpio_num, int value)
config |= value << bit;
outl(config, gpio_base + gpio_reg_offsets[index]);
}
+
+int gpio_is_native(int gpio_num)
+{
+ static const int gpio_reg_offsets[] = {
+ GPIO_USE_SEL, GPIO_USE_SEL2, GPIO_USE_SEL3
+ };
+ u16 gpio_base = get_gpio_base();
+ int index, bit;
+ u32 config;
+
+ if (gpio_num > MAX_GPIO_NUMBER)
+ return 0; /* Just ignore wrong gpio numbers. */
+
+ index = gpio_num / 32;
+ bit = gpio_num % 32;
+
+ config = inl(gpio_base + gpio_reg_offsets[index]);
+ return !(config & (1 << bit));
+}
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index 7d1a28d73c..cb052b22c3 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -159,3 +159,10 @@ void set_gpio(int gpio_num, int value)
conf0 |= value << GPO_LEVEL_SHIFT;
outl(conf0, gpio_base + GPIO_CONFIG0(gpio_num));
}
+
+int gpio_is_native(int gpio_num)
+{
+ u16 gpio_base = get_gpio_base();
+
+ return !(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & 1);
+}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index d1fbbe75bd..8ef7918df9 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -201,6 +201,8 @@ unsigned get_gpios(const int *gpio_num_array);
* set GPIO pin value
*/
void set_gpio(int gpio_num, int value);
+/* Return non-zero if gpio is set to native function. 0 otherwise. */
+int gpio_is_native(int gpio_num);
#endif
#define MAINBOARD_POWER_OFF 0