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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-10-05 13:40:31 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-10-05 13:40:31 +0000
commit5692c5733633bfb8b23f1111de152eff0233b713 (patch)
treed315817986c71d6710f75dceb87689b95e1bff53 /src/southbridge/intel
parentd0835953506263b0d9218b62176693315f2ef2f3 (diff)
downloadcoreboot-5692c5733633bfb8b23f1111de152eff0233b713.tar.xz
- move EHCI_BAR_INDEX to ehci.h - it's constant as per EHCI spec 2.3.1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges - drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig8
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h3
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx_usb_debug.c16
3 files changed, 19 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 556f526735..afee190b2d 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -24,3 +24,11 @@ config SOUTHBRIDGE_INTEL_I82801GX
select HAVE_USBDEBUG
select USE_WATCHDOG_ON_BOOT
+config EHCI_BAR
+ hex
+ default 0xfef00000 if SOUTHBRIDGE_INTEL_I82801GX
+
+config EHCI_DEBUG_OFFSET
+ hex
+ default 0xa0 if SOUTHBRIDGE_INTEL_I82801GX
+
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b5a2054526..559c896901 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -39,10 +39,13 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
+#if !defined(ASSEMBLY)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
#endif
+void i82801gx_enable_usbdebug(unsigned int port);
+#endif
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
diff --git a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
index 464dac2b92..991aa5adaa 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_usb_debug.c
@@ -18,12 +18,12 @@
*/
#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
#include <usbdebug.h>
#include <device/pci_def.h>
-
-#define EHCI_BAR 0xFEF00000 /* EHCI BAR address */
-#define EHCI_BAR_INDEX 0x10 /* Hardwired 0x10 (>= ICH4). */
-#define EHCI_DEBUG_OFFSET 0xA0 /* Hardwired 0xa0 (>= ICH5). */
+#include "i82801gx.h"
/* Required for successful build, but currently empty. */
void set_debug_port(unsigned int port)
@@ -31,20 +31,20 @@ void set_debug_port(unsigned int port)
/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
}
-static void i82801gx_enable_usbdebug(unsigned int port)
+void i82801gx_enable_usbdebug(unsigned int port)
{
u32 dbgctl;
device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
/* Set the EHCI BAR address. */
- pci_write_config32(dev, EHCI_BAR_INDEX, EHCI_BAR);
+ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
/* Enable access to the EHCI memory space registers. */
pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
/* Force ownership of the Debug Port to the EHCI controller. */
printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
- dbgctl = read32(EHCI_BAR + EHCI_DEBUG_OFFSET);
+ dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
dbgctl |= (1 << 30);
- write32(EHCI_BAR + EHCI_DEBUG_OFFSET, dbgctl);
+ write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
}