src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

53 files changed, 425 insertions, 427 deletions

diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index d5dcde08a4..c122d2a1c7 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 1000;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -145,7 +145,7 @@ static int wait_for_valid(u8 *base)
 	/* Use a 1msec timeout */
 
 	int timeout = 1000;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 1106912830..9041816ba1 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -125,7 +125,7 @@ static void pch_pirq_init(device_t dev)
 	pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
 	pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 83c99e0ee4..23915c3a80 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -445,7 +445,7 @@ static int mkhi_get_fwcaps(void)
 	print_cap("IntelR Power Sharing Technology (MPC)",
 		  cap.caps_sku.intel_mpc);
 	print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
 	print_cap("IPV6", cap.caps_sku.ipv6);
 	print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 4dbe8edd5b..220a176739 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -703,7 +703,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-		if(intel_me_read_mbp(&mbp_data))
+		if (intel_me_read_mbp(&mbp_data))
 			break;
 
 #if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -893,7 +893,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 		default:
 			printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n",
 			       mbp_item_id);
-			while(copy_size--)
+			while (copy_size--)
 				read_cb();
 			continue;
 		}
@@ -904,7 +904,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 			       buffer_room, copy_size, mbp_item_id);
 			return -1;
 		}
-		while(copy_size--)
+		while (copy_size--)
 			*copy_addr++ = read_cb();
 	}
 
@@ -914,7 +914,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	{
 		int cntr = 0;
-		while(host.interrupt_generate) {
+		while (host.interrupt_generate) {
 			read_host_csr(&host);
 			cntr++;
 		}
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index daabbbc8d6..804fb8137c 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -19,10 +19,10 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index bc19b78e1c..0478285195 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -271,37 +271,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 static void southbridge_gate_memory_reset_real(int offset,
@@ -863,7 +863,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c
index 5ec708ed77..b64d923125 100644
--- a/src/southbridge/intel/fsp_bd82x6x/azalia.c
+++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c
@@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index d12cd4e103..faec69a0db 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index 68a9ee55b8..a951f9f191 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
 	print_cap("IntelR Power Sharing Technology (MPC)",
 		  cap.caps_sku.intel_mpc);
 	print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
 	print_cap("IPV6", cap.caps_sku.ipv6);
 	print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index e29d86bf66..0d3a01e7c7 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -385,11 +385,10 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap)
 	};
 
 	/* Send request and wait for response */
-	if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg))
-	    < 0) {
+	if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) {
 		printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
 		return -1;
-        }
+	}
 	*cap = cap_msg.caps_sku;
 	return 0;
 }
@@ -413,7 +412,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
 	print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
 	print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
 	print_cap("ICC Over Clocking", cap->icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
 	print_cap("IPV6", cap->ipv6);
 	print_cap("KVM Remote Control (KVM)", cap->kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -702,7 +701,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-		if(intel_me_read_mbp(&mbp_data))
+		if (intel_me_read_mbp(&mbp_data))
 			break;
 
 #if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -901,7 +900,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 			       buffer_room, copy_size, mbp_item_id);
 			return -1;
 		}
-		while(copy_size--)
+		while (copy_size--)
 			*copy_addr++ = read_cb();
 	}
 
@@ -911,7 +910,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	{
 		int cntr = 0;
-		while(host.interrupt_generate) {
+		while (host.interrupt_generate) {
 			read_host_csr(&host);
 			cntr++;
 		}
diff --git a/src/southbridge/intel/fsp_bd82x6x/reset.c b/src/southbridge/intel/fsp_bd82x6x/reset.c
index c2e76d5ebc..a2e8236dc5 100644
--- a/src/southbridge/intel/fsp_bd82x6x/reset.c
+++ b/src/southbridge/intel/fsp_bd82x6x/reset.c
@@ -20,10 +20,10 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 77ada1083c..01ace5970f 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 /*
@@ -749,7 +749,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 5b8fdbcb6e..1514500e75 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c
index caf24e30fb..7ea42d4843 100644
--- a/src/southbridge/intel/fsp_i89xx/me.c
+++ b/src/southbridge/intel/fsp_i89xx/me.c
@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
 	print_cap("IntelR Power Sharing Technology (MPC)",
 		  cap.caps_sku.intel_mpc);
 	print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
 	print_cap("IPV6", cap.caps_sku.ipv6);
 	print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);
diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c
index 090d8d0f2b..f25843ed5c 100644
--- a/src/southbridge/intel/fsp_i89xx/me_8.x.c
+++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c
@@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
 	print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
 	print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
 	print_cap("ICC Over Clocking", cap->icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
 	print_cap("IPV6", cap->ipv6);
 	print_cap("KVM Remote Control (KVM)", cap->kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -670,7 +670,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-		if(intel_me_read_mbp(&mbp_data))
+		if (intel_me_read_mbp(&mbp_data))
 			break;
 
 #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
@@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 			       buffer_room, copy_size, mbp_item_id);
 			return -1;
 		}
-		while(copy_size--)
+		while (copy_size--)
 			*copy_addr++ = read_cb();
 	}
 
@@ -865,7 +865,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	{
 		int cntr = 0;
-		while(host.interrupt_generate) {
+		while (host.interrupt_generate) {
 			read_host_csr(&host);
 			cntr++;
 		}
diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index c5c1136a43..09cce59444 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -203,7 +203,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 
 	cbmem_was_initted = !cbmem_recovery(0);
 
-	if(cbmem_was_initted) {
+	if (cbmem_was_initted) {
 		reset_system();
 	}
 
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index 27b8166b1c..d4dbb22a94 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 /*
@@ -746,7 +746,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.c b/src/southbridge/intel/fsp_rangeley/gpio.c
index e57d85541e..2a2061cb1a 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.c
+++ b/src/southbridge/intel/fsp_rangeley/gpio.c
@@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
 	/* CFIO Core Well Set 1 */
 	if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
 		write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
-		for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
+		for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
 			if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
 				continue;
 			write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
@@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
 	/* CFIO SUS Well Set 1 */
 	if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
 		write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
-		for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
+		for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
 			if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
 				continue;
 			write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);
diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c
index 11aa60d60f..ab617506ef 100644
--- a/src/southbridge/intel/fsp_rangeley/lpc.c
+++ b/src/southbridge/intel/fsp_rangeley/lpc.c
@@ -137,7 +137,7 @@ static void write_pci_config_irqs(void)
 	 * the Interrupt Route registers in the ILB
 	 */
 	printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 
 		if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
 			(!irq_dev->enabled))
@@ -225,7 +225,7 @@ static void soc_pirq_init(device_t dev)
 		write16(ir_base + i, ir->pcidev[i]);
 
 		/* If the entry is more than just 0, print it out */
-		if(ir->pcidev[i]) {
+		if (ir->pcidev[i]) {
 			printk(BIOS_SPEW, " %d: ", i);
 			for (j = 0; j < 4; j++) {
 				pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;
diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index 12a9202e03..2cb241a138 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -27,7 +27,7 @@ static void enable_smbus(void)
 	pci_write_config8(dev, 0x40, 1);
 	pci_write_config8(dev, 0x4, 1);
 	/* SMBALERT_DIS */
-        outb(4, SMBUS_IO_BASE + SMBSLVCMD);
+	outb(4, SMBUS_IO_BASE + SMBSLVCMD);
 
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 77853a8631..7b319cf97c 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -206,19 +206,19 @@ static void i3100_pirq_init(device_t dev)
 	if (config->pirq_e_h)
 		pci_write_config32(dev, 0x68, config->pirq_e_h);
 
-        for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
-                u8 int_pin=0, int_line=0;
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+		u8 int_pin=0, int_line=0;
 
-                if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
-                        continue;
+		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+			continue;
 
-                int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-                switch (int_pin) {
-                case 1: /* INTA# */
+		int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+		switch (int_pin) {
+		case 1: /* INTA# */
 			int_line = config->pirq_a_d & 0xff;
 			break;
 
-                case 2: /* INTB# */
+		case 2: /* INTB# */
 			int_line = (config->pirq_a_d >> 8) & 0xff;
 			break;
 
@@ -226,17 +226,17 @@ static void i3100_pirq_init(device_t dev)
 			int_line = (config->pirq_a_d >> 16) & 0xff;
 			break;
 
-                case 4: /* INTD# */
+		case 4: /* INTD# */
 			int_line = (config->pirq_a_d >> 24) & 0xff;
 			break;
-                }
+		}
 
-                if (!int_line)
-                        continue;
+		if (!int_line)
+			continue;
 
 		printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line);
-                pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
-        }
+		pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+	}
 
 
 }
diff --git a/src/southbridge/intel/i3100/sata.c b/src/southbridge/intel/i3100/sata.c
index f4dff8bb79..27bd2ce141 100644
--- a/src/southbridge/intel/i3100/sata.c
+++ b/src/southbridge/intel/i3100/sata.c
@@ -42,7 +42,7 @@ static void sata_init(struct device *dev)
 	/* Enable SATA devices */
 	printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
 
-	if(ahci) {
+	if (ahci) {
 	  /* AHCI mode */
 	  pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
 
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 5b8d0edc5e..59d5dea104 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void)
 {
 	device_t cpu;
 	int count = 0;
-	for(cpu = all_devices; cpu; cpu = cpu->next) {
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
 			(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
 			continue;
diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h
index fd0221793e..de34504aff 100644
--- a/src/southbridge/intel/i82371eb/smbus.h
+++ b/src/southbridge/intel/i82371eb/smbus.h
@@ -35,12 +35,12 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 			break;
 		}
 #if 0
-		if(loops == (SMBUS_TIMEOUT / 2)) {
+		if (loops == (SMBUS_TIMEOUT / 2)) {
 			outw(inw(smbus_io_base + SMBHST_STATUS),
 				smbus_io_base + SMBHST_STATUS);
 		}
 #endif
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
@@ -62,7 +62,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 		if (val & 0xfe) {
 			break;
 		}
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
 
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index f4ab2f654f..a5581694f8 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -233,37 +233,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 
@@ -636,7 +636,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index 979b8420a5..ad543e7a94 100644
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -81,7 +81,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 	/* setup transaction */
 	/* Obtain ownership */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for(stat=0;(stat&0x40)==0;) {
+	for (stat=0;(stat&0x40)==0;) {
 	stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 	/* clear the done bit */
@@ -105,7 +105,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
 			SMBUS_IO_BASE + SMBHSTCTL);
 
-	for(i=0;i<length;i++) {
+	for (i=0;i<length;i++) {
 
 		/* poll for transaction completion */
 		if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
@@ -113,7 +113,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 		}
 
 		/* load the next byte */
-		if(i>3)
+		if (i>3)
 			byte=(data2>>(i%4))&0x0ff;
 		else
 			byte=(data1>>(i))&0x0ff;
diff --git a/src/southbridge/intel/i82801ex/lpc.c b/src/southbridge/intel/i82801ex/lpc.c
index 630484a6de..7d01dbc4ba 100644
--- a/src/southbridge/intel/i82801ex/lpc.c
+++ b/src/southbridge/intel/i82801ex/lpc.c
@@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev)
 #define LPC_EN 0xe6
 static void i82801ex_enable_lpc(device_t dev)
 {
-        /* lpc i/f enable */
-        pci_write_config8(dev, LPC_EN, 0x0d);
+	/* lpc i/f enable */
+	pci_write_config8(dev, LPC_EN, 0x0d);
 }
 
 typedef struct southbridge_intel_i82801ex_config config_t;
@@ -92,7 +92,7 @@ static void set_i82801ex_gpio_use_sel(
 
 	gpio_use_sel  = 0x1A003180;
 	gpio_use_sel2 = 0x00000007;
-	for(i = 0; i < 64; i++) {
+	for (i = 0; i < 64; i++) {
 		int val;
 		switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
 		case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
@@ -121,7 +121,7 @@ static void set_i82801ex_gpio_direction(
 
 	gpio_io_sel  = 0x0000ffff;
 	gpio_io_sel2 = 0x00000300;
-	for(i = 0; i < 64; i++) {
+	for (i = 0; i < 64; i++) {
 		int val;
 		switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
 		case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
@@ -152,7 +152,7 @@ static void set_i82801ex_gpio_level(
 	gpio_lvl   = 0x1b3f0000;
 	gpio_blink = 0x00040000;
 	gpio_lvl2  = 0x00030207;
-	for(i = 0; i < 64; i++) {
+	for (i = 0; i < 64; i++) {
 		int val, blink;
 		switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
 		case ICH5R_GPIO_LVL_LOW:   val = 0; blink = 0; break;
@@ -184,7 +184,7 @@ static void set_i82801ex_gpio_inv(
 	int i;
 
 	gpio_inv   = 0x00000000;
-	for(i = 0; i < 32; i++) {
+	for (i = 0; i < 32; i++) {
 		int val;
 		switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
 		case ICH5R_GPIO_INV_OFF: val = 0; break;
@@ -205,10 +205,10 @@ static void i82801ex_pirq_init(device_t dev)
 	/* Get the chip configuration */
 	config = dev->chip_info;
 
-	if(config->pirq_a_d) {
+	if (config->pirq_a_d) {
 		pci_write_config32(dev, 0x60, config->pirq_a_d);
 	}
-	if(config->pirq_e_h) {
+	if (config->pirq_e_h) {
 		pci_write_config32(dev, 0x68, config->pirq_e_h);
 	}
 }
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
 	/* Clear SATA to non raid */
 	pci_write_config8(dev, 0xae, 0x00);
 
-        get_option(&pwr_on, "power_on_after_fail");
+	get_option(&pwr_on, "power_on_after_fail");
 	byte = pci_read_config8(dev, 0xa4);
 	byte &= 0xfe;
 	if (!pwr_on) {
diff --git a/src/southbridge/intel/i82801ex/reset.c b/src/southbridge/intel/i82801ex/reset.c
index 9936892efe..8036ffde17 100644
--- a/src/southbridge/intel/i82801ex/reset.c
+++ b/src/southbridge/intel/i82801ex/reset.c
@@ -3,6 +3,6 @@
 
 void hard_reset(void)
 {
-        /* Try rebooting through port 0xcf9 */
-        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+	/* Try rebooting through port 0xcf9 */
+	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
 }
diff --git a/src/southbridge/intel/i82801ex/smbus.h b/src/southbridge/intel/i82801ex/smbus.h
index b166797600..dbb7b7a416 100644
--- a/src/southbridge/intel/i82801ex/smbus.h
+++ b/src/southbridge/intel/i82801ex/smbus.h
@@ -29,7 +29,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 		if (--loops == 0)
 			break;
 		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while(byte & 1);
+	} while (byte & 1);
 	return loops?0:-1;
 }
 
@@ -42,7 +42,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	        if (--loops == 0)
 	               break;
 	        byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+	} while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
 	return loops?0:-1;
 }
 
@@ -55,7 +55,7 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
 	        if (--loops == 0)
 	               break;
 	        byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while((byte&(1<<7)) == 0);
+	} while ((byte&(1<<7)) == 0);
 	return loops?0:-1;
 }
 
diff --git a/src/southbridge/intel/i82801ex/watchdog.c b/src/southbridge/intel/i82801ex/watchdog.c
index 28e1f5e2f2..6aba2703cb 100644
--- a/src/southbridge/intel/i82801ex/watchdog.c
+++ b/src/southbridge/intel/i82801ex/watchdog.c
@@ -6,23 +6,23 @@
 
 void watchdog_off(void)
 {
-        device_t dev;
-        unsigned long value,base;
+	device_t dev;
+	unsigned long value,base;
 
 	/* turn off the ICH5 watchdog */
-        dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-        /* Enable I/O space */
-        value = pci_read_config16(dev, 0x04);
-        value |= (1 << 10);
-        pci_write_config16(dev, 0x04, value);
-        /* Get TCO base */
-        base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-        /* Disable the watchdog timer */
-        value = inw(base + 0x08);
-        value |= 1 << 11;
-        outw(value, base + 0x08);
-        /* Clear TCO timeout status */
-        outw(0x0008, base + 0x04);
-        outw(0x0002, base + 0x06);
-        printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	/* Enable I/O space */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
+	/* Get TCO base */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+	/* Disable the watchdog timer */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+	/* Clear TCO timeout status */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+	printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
 }
diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c
index d28154c0df..b13d809d5f 100644
--- a/src/southbridge/intel/i82801gx/azalia.c
+++ b/src/southbridge/intel/i82801gx/azalia.c
@@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -146,7 +146,7 @@ static int wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index 50268b6883..c9c19a3b78 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -30,22 +30,22 @@ static void store_initial_timestamp(void)
 
 static void enable_spi_prefetch(void)
 {
-        u8 reg8;
-        pci_devfn_t dev;
+	u8 reg8;
+	pci_devfn_t dev;
 
-        dev = PCI_DEV(0, 0x1f, 0);
+	dev = PCI_DEV(0, 0x1f, 0);
 
-        reg8 = pci_read_config8(dev, 0xdc);
-        reg8 &= ~(3 << 2);
-        reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-        pci_write_config8(dev, 0xdc, reg8);
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
 }
 
 static void bootblock_southbridge_init(void)
 {
 	store_initial_timestamp();
 
-        enable_spi_prefetch();
+	enable_spi_prefetch();
 
 	/* Enable RCBA */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 03df1a3a08..280e207e11 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -108,7 +108,7 @@ static void i82801gx_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/i82801gx/reset.c b/src/southbridge/intel/i82801gx/reset.c
index 39c4f31619..97b82251f0 100644
--- a/src/southbridge/intel/i82801gx/reset.c
+++ b/src/southbridge/intel/i82801gx/reset.c
@@ -19,7 +19,7 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 #if 0
@@ -32,6 +32,6 @@ void hard_reset(void)
 
 void hard_reset(void)
 {
-        outb(0x02, 0xcf9);
-        outb(0x06, 0xcf9);
+	outb(0x02, 0xcf9);
+	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index 913f68f74b..e6aa01885a 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -123,7 +123,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
 	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
 	     smbus_base + SMBHSTCTL);
 
-	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	while (!(inb(smbus_base + SMBHSTSTAT) & 1));
 	/* Poll for transaction completion */
 	do {
 		status = inb(smbus_base + SMBHSTSTAT);
@@ -136,7 +136,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
 			outb(*buf++, smbus_base + SMBBLKDAT);
 			outb(status, smbus_base + SMBHSTSTAT);
 		}
-	} while(status & 0x01);
+	} while (status & 0x01);
 
 	return 0;
 }
@@ -180,7 +180,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
 	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
 	     smbus_base + SMBHSTCTL);
 
-	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	while (!(inb(smbus_base + SMBHSTSTAT) & 1));
 	/* Poll for transaction completion */
 	do {
 		status = inb(smbus_base + SMBHSTSTAT);
@@ -200,7 +200,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
 					 smbus_base + SMBHSTCTL);
 			}
 		}
-	} while(status & 0x01);
+	} while (status & 0x01);
 
 	return bytes_read;
 }
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index e76087cf21..d3867a5950 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -269,37 +269,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 
@@ -673,7 +673,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index e2223686ba..6252712eba 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -17,18 +17,18 @@
 
 static void enable_spi_prefetch(void)
 {
-        u8 reg8;
-        pci_devfn_t dev;
+	u8 reg8;
+	pci_devfn_t dev;
 
-        dev = PCI_DEV(0, 0x1f, 0);
+	dev = PCI_DEV(0, 0x1f, 0);
 
-        reg8 = pci_read_config8(dev, 0xdc);
-        reg8 &= ~(3 << 2);
-        reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-        pci_write_config8(dev, 0xdc, reg8);
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
 }
 
 static void bootblock_southbridge_init(void)
 {
-        enable_spi_prefetch();
+	enable_spi_prefetch();
 }
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c
index 4848b948b8..c3602c40b0 100644
--- a/src/southbridge/intel/i82801ix/hdaudio.c
+++ b/src/southbridge/intel/i82801ix/hdaudio.c
@@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 4415f44154..e095ad8622 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -110,7 +110,7 @@ static void i82801ix_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 5f1a44f5b9..7ad00ed5ba 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -518,7 +518,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c
index 6a0f0d222f..a02a2afde6 100644
--- a/src/southbridge/intel/i82870/ioapic.c
+++ b/src/southbridge/intel/i82870/ioapic.c
@@ -11,11 +11,10 @@ static int num_p64h2_ioapics = 0;
 
 static void p64h2_ioapic_enable(device_t dev)
 {
-    /* We have to enable MEM and Bus Master for IOAPIC */
-    uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	/* We have to enable MEM and Bus Master for IOAPIC */
+	uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 
-
-    pci_write_config16(dev, PCI_COMMAND, command);
+	pci_write_config16(dev, PCI_COMMAND, command);
 }
 
 /**
@@ -29,70 +28,70 @@ static void p64h2_ioapic_enable(device_t dev)
  */
 static void p64h2_ioapic_init(device_t dev)
 {
-    uint32_t memoryBase;
-    int apic_index, apic_id;
+	uint32_t memoryBase;
+	int apic_index, apic_id;
 
-    volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
-    volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
+	volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
+	volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
 
-    apic_index = num_p64h2_ioapics;
-    num_p64h2_ioapics++;
+	apic_index = num_p64h2_ioapics;
+	num_p64h2_ioapics++;
 
-    // A note on IOAPIC addresses:
-    //  0 and 1 are used for the local APICs of the dual virtual
-    //  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
-    //  6 and 7 are used for the local APICs of the dual virtual
-    //  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
-    //  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
+	// A note on IOAPIC addresses:
+	//  0 and 1 are used for the local APICs of the dual virtual
+	//  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
+	//  6 and 7 are used for the local APICs of the dual virtual
+	//  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
+	//  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
 
-    // Map APIC index into APIC ID
-    // IDs 3, 4, 5, and 8+ are available (see above note)
+	// Map APIC index into APIC ID
+	// IDs 3, 4, 5, and 8+ are available (see above note)
 
-    if (apic_index < 3)
-        apic_id = apic_index + 3;
-    else
-        apic_id = apic_index + 5;
+	if (apic_index < 3)
+		apic_id = apic_index + 3;
+	else
+		apic_id = apic_index + 5;
 
-    ASSERT(apic_id < 16);       // ID is only 4 bits
+	ASSERT(apic_id < 16);       // ID is only 4 bits
 
-    // Read the MBAR address for setting up the IOAPIC in memory space
-    // NOTE: this address was assigned during enumeration of the bus
+	// Read the MBAR address for setting up the IOAPIC in memory space
+	// NOTE: this address was assigned during enumeration of the bus
 
-    memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-    pIndexRegister  = (volatile uint32_t*) memoryBase;
-    pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
+	memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	pIndexRegister  = (volatile uint32_t*) memoryBase;
+	pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
 
-    printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
-                 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
-                 PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
+	printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
+		apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+		PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
 
-    apic_id <<= 24;             // Convert ID to bitmask
+	apic_id <<= 24;             // Convert ID to bitmask
 
-    *pIndexRegister = 0;        // Select APIC ID register
-    *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
+	*pIndexRegister = 0;        // Select APIC ID register
+	*pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
 
-    if ((*pWindowRegister & (0xF<<24)) != apic_id)
-        die("p64h2_ioapic_init failed");
+	if ((*pWindowRegister & (0xF<<24)) != apic_id)
+		die("p64h2_ioapic_init failed");
 
-    *pIndexRegister  = 3;   // Select Boot Configuration register
-    *pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
+	*pIndexRegister  = 3;   // Select Boot Configuration register
+	*pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
 
-    if (!(*pWindowRegister & 1))
-        die("p64h2_ioapic_init failed");
+	if (!(*pWindowRegister & 1))
+		die("p64h2_ioapic_init failed");
 }
 
 static struct device_operations ioapic_ops = {
-        .read_resources   = pci_dev_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
-        .init     = p64h2_ioapic_init,
-        .scan_bus = 0,
-        .enable   = p64h2_ioapic_enable,
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init     = p64h2_ioapic_init,
+	.scan_bus = 0,
+	.enable   = p64h2_ioapic_enable,
 };
 
 static const struct pci_driver ioapic_driver __pci_driver = {
-        .ops    = &ioapic_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82870_1E0,
+	.ops    = &ioapic_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82870_1E0,
 
 };
diff --git a/src/southbridge/intel/i82870/pci_parity.c b/src/southbridge/intel/i82870/pci_parity.c
index 71d2c538e9..b886c5244f 100644
--- a/src/southbridge/intel/i82870/pci_parity.c
+++ b/src/southbridge/intel/i82870/pci_parity.c
@@ -5,19 +5,19 @@
 
 void p64h2_pci_parity_enable(void)
 {
-        uint8_t reg;
+	uint8_t reg;
 
-        /* 2SERREN - SERR enable for PCI bridge secondary device  */
-        /* 2PEREN  - Parity error for PCI bridge secondary device  */
-        pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
-        reg |= ((1 << 1) + (1 << 0));
-        pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
+	/* 2SERREN - SERR enable for PCI bridge secondary device  */
+	/* 2PEREN  - Parity error for PCI bridge secondary device  */
+	pcibios_read_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, &reg);
+	reg |= ((1 << 1) + (1 << 0));
+	pcibios_write_config_byte(1, ((29 << 3) + (0 << 0)), 0x3e, reg);
 
-        /* 2SERREN - SERR enable for PCI bridge secondary device  */
-        /* 2PEREN  - Parity error for PCI bridge secondary device  */
-        pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
-        reg |= ((1 << 1) + (1 << 0));
-        pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
+	/* 2SERREN - SERR enable for PCI bridge secondary device  */
+	/* 2PEREN  - Parity error for PCI bridge secondary device  */
+	pcibios_read_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, &reg);
+	reg |= ((1 << 1) + (1 << 0));
+	pcibios_write_config_byte(1, ((31 << 3) + (0 << 0)), 0x3e, reg);
 
-        return;
+	return;
 }
diff --git a/src/southbridge/intel/i82870/pcibridge.c b/src/southbridge/intel/i82870/pcibridge.c
index b46b3381ab..e8d890ab95 100644
--- a/src/southbridge/intel/i82870/pcibridge.c
+++ b/src/southbridge/intel/i82870/pcibridge.c
@@ -23,16 +23,16 @@ static void p64h2_pcix_init(device_t dev)
 
 }
 static struct device_operations pcix_ops  = {
-        .read_resources   = pci_bus_read_resources,
-        .set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_bus_enable_resources,
-        .init             = p64h2_pcix_init,
-        .scan_bus         = pci_scan_bridge,
+	.read_resources   = pci_bus_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_bus_enable_resources,
+	.init             = p64h2_pcix_init,
+	.scan_bus         = pci_scan_bridge,
 	.reset_bus        = pci_bus_reset,
 };
 
 static const struct pci_driver pcix_driver __pci_driver = {
-        .ops    = &pcix_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82870_1F0,
+	.ops    = &pcix_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = PCI_DEVICE_ID_INTEL_82870_1F0,
 };
diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c
index dfcbcb60a6..d9f635a925 100644
--- a/src/southbridge/intel/ibexpeak/azalia.c
+++ b/src/southbridge/intel/ibexpeak/azalia.c
@@ -115,7 +115,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 1000;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -143,7 +143,7 @@ static int wait_for_valid(u8 *base)
 	/* Use a 1msec timeout */
 
 	int timeout = 1000;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 88ec851582..23b192575f 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -120,7 +120,7 @@ static void pch_pirq_init(device_t dev)
 	pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
 	pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c
index e7681fb3cb..19ef098808 100644
--- a/src/southbridge/intel/ibexpeak/sata.c
+++ b/src/southbridge/intel/ibexpeak/sata.c
@@ -126,7 +126,7 @@ static void sata_init(struct device *dev)
 		reg32 &= ~0x00000005;
 		write32(abar + 0x28, reg32);
 	} else {
-                /* IDE */
+		/* IDE */
 		printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
 
 		/* No AHCI: clear AHCI base */
diff --git a/src/southbridge/intel/ibexpeak/smbus.h b/src/southbridge/intel/ibexpeak/smbus.h
index aeac5732ab..0815bf4f14 100644
--- a/src/southbridge/intel/ibexpeak/smbus.h
+++ b/src/southbridge/intel/ibexpeak/smbus.h
@@ -171,7 +171,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
 	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
 	     smbus_base + SMBHSTCTL);
 
-	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	while (!(inb(smbus_base + SMBHSTSTAT) & 1));
 	/* Poll for transaction completion */
 	do {
 		status = inb(smbus_base + SMBHSTSTAT);
@@ -184,7 +184,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
 			outb(*buf++, smbus_base + SMBBLKDAT);
 			outb(status, smbus_base + SMBHSTSTAT);
 		}
-	} while(status & 0x01);
+	} while (status & 0x01);
 
 	return 0;
 }
@@ -214,7 +214,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
 	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
 	     smbus_base + SMBHSTCTL);
 
-	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	while (!(inb(smbus_base + SMBHSTSTAT) & 1));
 	/* Poll for transaction completion */
 	do {
 		status = inb(smbus_base + SMBHSTSTAT);
@@ -234,7 +234,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
 					 smbus_base + SMBHSTCTL);
 			}
 		}
-	} while(status & 0x01);
+	} while (status & 0x01);
 
 	return bytes_read;
 }
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d11d531777..0ad7e658fc 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -273,37 +273,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 static void southbridge_gate_memory_reset_real(int offset,
@@ -849,7 +849,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
index 96ab34e474..a8a139c40c 100644
--- a/src/southbridge/intel/lynxpoint/hda_verb.c
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -94,7 +94,7 @@ static int hda_wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base +  HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -122,7 +122,7 @@ static int hda_wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 1d20bbbe3b..f8ec94ec1f 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -124,7 +124,7 @@ static void pch_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
@@ -194,7 +194,7 @@ static void pch_power_options(device_t dev)
 	 * If the option is not existent (Laptops), use Kconfig setting.
 	 */
 	get_option(&pwr_on, "power_on_after_fail");
-        pwr_on = MAINBOARD_POWER_KEEP;
+	pwr_on = MAINBOARD_POWER_KEEP;
 
 	reg16 = pci_read_config16(dev, GEN_PMCON_3);
 	reg16 &= 0xfffe;
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 43e5289dfa..355db4b6e1 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -485,7 +485,7 @@ static int mkhi_get_fwcaps(mbp_mefwcaps *cap)
 			      &cap_msg, sizeof(cap_msg)) < 0) {
 		printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
 		return -1;
-        }
+	}
 	*cap = cap_msg.caps_sku;
 	return 0;
 }
@@ -650,7 +650,7 @@ static int me_icc_set_clock_enables(u32 mask)
 	if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
 		printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
 		return -1;
-        } else {
+	} else {
 		printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
 	}
 
diff --git a/src/southbridge/intel/lynxpoint/reset.c b/src/southbridge/intel/lynxpoint/reset.c
index daabbbc8d6..804fb8137c 100644
--- a/src/southbridge/intel/lynxpoint/reset.c
+++ b/src/southbridge/intel/lynxpoint/reset.c
@@ -19,10 +19,10 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 4f0db1b90c..0102308812 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -68,37 +68,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
-        unsigned int val;
-        unsigned char hdr;
-
-        for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
-                        u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
-
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
-
-                        if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
-                                continue;
-
-                        /* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
-
-                        /* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
-                }
-        }
+	int slot, func;
+	unsigned int val;
+	unsigned char hdr;
+
+	for (slot = 0; slot < 0x20; slot++) {
+		for (func = 0; func < 8; func++) {
+			u32 reg32;
+			device_t dev = PCI_DEV(bus, slot, func);
+
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+			if (val == 0xffffffff || val == 0x00000000 ||
+			    val == 0x0000ffff || val == 0xffff0000)
+				continue;
+
+			/* Disable Bus Mastering for this one device */
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 &= ~PCI_COMMAND_MASTER;
+			pci_write_config32(dev, PCI_COMMAND, reg32);
+
+			/* If this is a bridge, then follow it. */
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr &= 0x7f;
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
+				unsigned int buses;
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
+			}
+		}
+	}
 }
 
 
@@ -459,7 +459,7 @@ static void southbridge_smi_monitor(void)
 	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n",
 	       trap_cycle & 0xfffc);
 	for (i=0; i < 4; i++)
-		if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+		if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
 	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
 	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
 	printk(BIOS_DEBUG, "  read/write: %s\n",