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authorWim Vervoorn <wvervoorn@eltan.com>2020-01-15 11:31:25 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-01-22 15:41:02 +0000
commitbccc7e707201833215d2c002533b3e05443ca298 (patch)
tree3f6a28a94c1a0c8522f34e29abc37b474a7938cd /src/southbridge/intel
parent951a6207f32fbfc7bf21f122b3a66b88fb79892c (diff)
downloadcoreboot-bccc7e707201833215d2c002533b3e05443ca298.tar.xz
{soc,southbridge}/*/*/acpi: Add possibility to disable S4
Some boards don't support S3 or S4. The S4 state can't be removed from the available sleep states. Add a config item that allows removal of the S4 state from the list of available sleep states. The S4 state can be removed by selecting the item on board level. For the AMD chipsets the SSFG mask is updated to remove the S4 state. BUG=N/A TEST=build Change-Id: Id802c4cc40308ddf39e99e7f226d55e0e020f0c9 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38431 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/acpi/sleepstates.asl2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl
index 79818a109a..32cc22bd39 100644
--- a/src/southbridge/intel/common/acpi/sleepstates.asl
+++ b/src/southbridge/intel/common/acpi/sleepstates.asl
@@ -20,5 +20,7 @@ Name(\_S1, Package(){0x1,0x0,0x0,0x0})
#else
Name(\_S3, Package(){0x5,0x0,0x0,0x0})
#endif
+#if !CONFIG(DISABLE_ACPI_HIBERNATE)
Name(\_S4, Package(){0x6,0x0,0x0,0x0})
+#endif
Name(\_S5, Package(){0x7,0x0,0x0,0x0})