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authorDuncan Laurie <dlaurie@chromium.org>2013-12-17 15:35:51 -0800
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-09-18 18:31:25 +0200
commitd5acaaf8451d727107b53882c9d3bae4482fe0b8 (patch)
tree06e436cb7f941c5da100455f1306a91c9f200937 /src/southbridge/intel
parent51d787a5cf8b65aff0800743437443e416845655 (diff)
downloadcoreboot-d5acaaf8451d727107b53882c9d3bae4482fe0b8.tar.xz
lynxpoint: Don't enable SMI handling of TCO
We have no good reason to be handling the TCO timeout as an SMI since we aren't doing anything special with it and clearing the status in the handler prevents the reboot from actually happening. Change-Id: I074ac0cfa7230606690e3f0e4c40ebc2a8713635 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180672 (cherry picked from commit 608a2c5768e9300c81b7c72fb8ab7a0c7c142bec) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6907 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index af40eaf020..94abf5f700 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -64,14 +64,14 @@ void southbridge_smm_enable_smi(void)
disable_gpe(PME_B0_EN);
/* Enable SMI generation:
- * - on TCO events
* - on APMC writes (io 0xb2)
* - on writes to SLP_EN (sleep states)
* - on writes to GBL_RLS (bios commands)
* No SMIs:
* - on microcontroller writes (io 0x62/0x66)
+ * - on TCO events
*/
- enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
+ enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
void southbridge_trigger_smi(void)