src/*/intel/: clarify Kconfig options regarding IFD

HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.

Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.

Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.

Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

10 files changed, 19 insertions, 10 deletions

diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index c028595e9c..16602cf883 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -37,7 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_COMMON_CLOCK
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select RTC
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 4f8a407490..73e01cdcc4 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -25,6 +25,12 @@ config HAVE_INTEL_CHIPSET_LOCKDOWN
 config SOUTHBRIDGE_INTEL_COMMON_SMM
 	def_bool n
 
+config INTEL_DESCRIPTOR_MODE_CAPABLE
+	def_bool n
+	help
+	  This config simply states that the platform is *capable* of running in
+	  descriptor mode (when the descriptor in flash is valid).
+
 config INTEL_CHIPSET_LOCKDOWN
 	depends on HAVE_INTEL_CHIPSET_LOCKDOWN && HAVE_SMI_HANDLER && !CHROMEOS
 	#ChromeOS's payload seems to handle finalization on its on.
diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig
index 590d120385..97fb99320a 100644
--- a/src/southbridge/intel/common/firmware/Kconfig
+++ b/src/southbridge/intel/common/firmware/Kconfig
@@ -16,9 +16,12 @@
 
 config HAVE_INTEL_FIRMWARE
 	bool
+	default y if INTEL_DESCRIPTOR_MODE_CAPABLE
 	help
-	  Chipset uses the Intel Firmware Descriptor to describe the
-	  layout of the SPI ROM chip.
+	  Platform uses the Intel Firmware Descriptor to describe the
+	  layout of the SPI ROM chip. Enabling this option will allow you to
+	  select further features that rely on this like providing individual
+	  firmware blobs.
 
 if HAVE_INTEL_FIRMWARE
 
diff --git a/src/southbridge/intel/fsp_bd82x6x/Kconfig b/src/southbridge/intel/fsp_bd82x6x/Kconfig
index 877a335545..cf693f6812 100644
--- a/src/southbridge/intel/fsp_bd82x6x/Kconfig
+++ b/src/southbridge/intel/fsp_bd82x6x/Kconfig
@@ -29,7 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select COMMON_FADT
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 	select SOUTHBRIDGE_INTEL_COMMON_SPI
diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig
index d0cb45c250..9dd62ed742 100644
--- a/src/southbridge/intel/fsp_i89xx/Kconfig
+++ b/src/southbridge/intel/fsp_i89xx/Kconfig
@@ -29,7 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select COMMON_FADT
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select NO_EARLY_BOOTBLOCK_POSTCODES
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
diff --git a/src/southbridge/intel/fsp_rangeley/Kconfig b/src/southbridge/intel/fsp_rangeley/Kconfig
index ab85ec4c97..3cd5861e00 100644
--- a/src/southbridge/intel/fsp_rangeley/Kconfig
+++ b/src/southbridge/intel/fsp_rangeley/Kconfig
@@ -29,7 +29,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
 	select SPI_FLASH
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOUTHBRIDGE_INTEL_COMMON
 	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
 
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 236b43ace1..9e88a2830b 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -27,7 +27,7 @@ config SOUTHBRIDGE_INTEL_I82801IX
 	select HAVE_USBDEBUG_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select SOUTHBRIDGE_INTEL_COMMON_SMM
-	select HAVE_INTEL_FIRMWARE if !BOARD_EMULATION_QEMU_X86_Q35
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
 
 if SOUTHBRIDGE_INTEL_I82801IX
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 2c98f72e4b..bf2d01fb20 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -27,7 +27,7 @@ config SOUTHBRIDGE_INTEL_I82801JX
 	select HAVE_SMI_HANDLER
 	select HAVE_USBDEBUG_OPTIONS
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select COMMON_FADT
 
 if SOUTHBRIDGE_INTEL_I82801JX
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index d377950818..5b085b7e1d 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -35,7 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select HAVE_USBDEBUG_OPTIONS
 	select COMMON_FADT
 	select ACPI_SATA_GENERATOR
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO
 	select HAVE_INTEL_CHIPSET_LOCKDOWN
 
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index ee870fcd01..dc25b850d8 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -30,7 +30,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy
 	select USE_WATCHDOG_ON_BOOT
 	select PCIEXP_ASPM
 	select PCIEXP_COMMON_CLOCK
-	select HAVE_INTEL_FIRMWARE
+	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SPI_CONSOLE_SUPPORT
 	select RTC
 	select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP