diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 18:11:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-18 11:47:58 +0000 |
| commit | 360d94745feea766de7ef19487ba9158221faca0 (patch) | |
| tree | 757402cd145f8f791cfa9594570e4d2a5d5f026c /src/southbridge/intel | |
| parent | 67d59d1756423a96aca5249b59c4e3759b2f3721 (diff) | |
| download | coreboot-360d94745feea766de7ef19487ba9158221faca0.tar.xz | |
nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCK
There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/bootblock.c | 16 |
3 files changed, 8 insertions, 15 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c01e2b9eed..1c7e9b7da6 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -57,10 +57,6 @@ config DRAM_RESET_GATE_GPIO int default 60 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/bd82x6x/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index b23fa7a327..5140d23388 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -15,6 +15,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_C216)$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X),y) +bootblock-y += bootblock.c +bootblock-y += early_pch.c + ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 0086fe3281..1a8242f8d4 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <cpu/intel/car/bootblock.h> #include <device/pci_ops.h> #include "pch.h" @@ -32,18 +33,8 @@ static void enable_spi_prefetch(void) static void enable_port80_on_lpc(void) { - pci_devfn_t dev = PCH_LPC_DEV; - /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -#if 0 RCBA32(GCS) &= (~0x04); -#else - volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); - u32 reg32 = *gcs; - reg32 = reg32 & ~0x04; - *gcs = reg32; -#endif } static void set_spi_speed(void) @@ -66,9 +57,12 @@ static void set_spi_speed(void) RCBA8(0x3893) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); + + early_pch_init(); + enable_port80_on_lpc(); set_spi_speed(); |