cpu/intel: Use the common code to initialize the romstage timestamps

The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

10 files changed, 0 insertions, 125 deletions

diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85419030b4..673f0c74af 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "pch.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On Cougar Point we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 /*
  * Enable Prefetching and Caching.
  */
@@ -80,8 +68,6 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	enable_spi_prefetch();
 	enable_port80_on_lpc();
 	set_spi_speed();
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index 3e151fcb75..a9ec9b1a2c 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -15,8 +15,6 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include "pch.h"
@@ -25,15 +23,6 @@
 #include <rules.h>
 
 #if ENV_ROMSTAGE
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 pm1_cnt;
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index c9c19a3b78..6d65df3983 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "i82801gx.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On i945/ICH7 we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
@@ -43,8 +31,6 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	enable_spi_prefetch();
 
 	/* Enable RCBA */
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c
index 11da3ec4b1..a52fb8512e 100644
--- a/src/southbridge/intel/i82801gx/early_lpc.c
+++ b/src/southbridge/intel/i82801gx/early_lpc.c
@@ -15,21 +15,10 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include "i82801gx.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 reg32;
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index bb025b0eae..6252712eba 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -14,19 +14,6 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
-
-static void store_initial_timestamp(void)
-{
-	/*
-	 * We have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
 
 static void enable_spi_prefetch(void)
 {
@@ -43,6 +30,5 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
 	enable_spi_prefetch();
 }
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index 7c4dafaef6..c40f9b73ea 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -15,19 +15,8 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include "i82801ix.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 void i82801ix_early_init(void)
 {
 	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c
index 115555c599..cc685c4544 100644
--- a/src/southbridge/intel/i82801jx/bootblock.c
+++ b/src/southbridge/intel/i82801jx/bootblock.c
@@ -14,21 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "i82801jx.h"
 
-static void store_initial_timestamp(void)
-{
-	/*
-	 * We have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
@@ -44,7 +31,6 @@ static void enable_spi_prefetch(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
 	enable_spi_prefetch();
 
 	/* Enable RCBA */
diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c
index 74f0ee2920..a59fdccedc 100644
--- a/src/southbridge/intel/i82801jx/early_lpc.c
+++ b/src/southbridge/intel/i82801jx/early_lpc.c
@@ -15,21 +15,10 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include "i82801jx.h"
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 reg32;
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 1a9e7bba61..cb595cdd0c 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -14,20 +14,8 @@
  */
 
 #include <arch/io.h>
-#include <cpu/x86/tsc.h>
 #include "pch.h"
 
-static void store_initial_timestamp(void)
-{
-	/* On Cougar Point we have two 32bit scratchpad registers available:
-	 * D0:F0  0xdc (SKPAD)
-	 * D31:F2 0xd0 (SATA SP)
-	 */
-	tsc_t tsc = rdtsc();
-	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
-	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
-}
-
 /*
  * Enable Prefetching and Caching.
  */
@@ -83,8 +71,6 @@ static void set_spi_speed(void)
 
 static void bootblock_southbridge_init(void)
 {
-	store_initial_timestamp();
-
 	map_rcba();
 	enable_spi_prefetch();
 	enable_port80_on_lpc();
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 46e803d82f..912df8ea4c 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -18,8 +18,6 @@
 #include <arch/io.h>
 #include <device/device.h>
 #include <device/pci_def.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <elog.h>
 #include "pch.h"
 #include "chip.h"
@@ -68,15 +66,6 @@ static void pch_generic_setup(void)
 	printk(BIOS_DEBUG, " done.\n");
 }
 
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 static int sleep_type_s3(void)
 {
 	u32 pm1_cnt;