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authorElyes HAOUAS <ehaouas@noos.fr>2016-08-21 18:36:06 +0200
committerMartin Roth <martinroth@google.com>2016-08-28 18:26:07 +0200
commit70d79a454676b551f3bc2059217179e31905ee5c (patch)
tree1a27cd7c57a9d46d0c7d6e7aaeb361c73dfac872 /src/southbridge/intel
parent03b040b95f1a16d07b98e15c1aeef77ec7a4eca9 (diff)
downloadcoreboot-70d79a454676b551f3bc2059217179e31905ee5c.tar.xz
src/southbridge: Add required space before opening parenthesis '('
Change-Id: I43b9b86fd51dbdc50108026099c60238f3012cbe Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16290 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/sata.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/smihandler.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/sata.c2
-rw-r--r--src/southbridge/intel/fsp_i89xx/smihandler.c2
-rw-r--r--src/southbridge/intel/fsp_rangeley/sata.c2
-rw-r--r--src/southbridge/intel/i3100/lpc.c6
-rw-r--r--src/southbridge/intel/i82801dx/smihandler.c2
-rw-r--r--src/southbridge/intel/i82801ex/i82801ex.c4
-rw-r--r--src/southbridge/intel/i82801gx/sata.c2
-rw-r--r--src/southbridge/intel/i82801gx/smihandler.c2
-rw-r--r--src/southbridge/intel/i82801ix/smihandler.c2
-rw-r--r--src/southbridge/intel/ibexpeak/smihandler.c2
-rw-r--r--src/southbridge/intel/lynxpoint/sata.c2
14 files changed, 17 insertions, 17 deletions
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index e4e5b81493..bc19b78e1c 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -782,7 +782,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c
index 81a5d7de53..6130646629 100644
--- a/src/southbridge/intel/fsp_bd82x6x/sata.c
+++ b/src/southbridge/intel/fsp_bd82x6x/sata.c
@@ -52,7 +52,7 @@ static void sata_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
index 987d6d1e1f..77ada1083c 100644
--- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c
+++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c
@@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/fsp_i89xx/sata.c b/src/southbridge/intel/fsp_i89xx/sata.c
index 87d5431f45..810847a861 100644
--- a/src/southbridge/intel/fsp_i89xx/sata.c
+++ b/src/southbridge/intel/fsp_i89xx/sata.c
@@ -52,7 +52,7 @@ static void sata_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c
index e0d19d685f..27b8166b1c 100644
--- a/src/southbridge/intel/fsp_i89xx/smihandler.c
+++ b/src/southbridge/intel/fsp_i89xx/smihandler.c
@@ -666,7 +666,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/fsp_rangeley/sata.c b/src/southbridge/intel/fsp_rangeley/sata.c
index 4861f838c9..624af23b49 100644
--- a/src/southbridge/intel/fsp_rangeley/sata.c
+++ b/src/southbridge/intel/fsp_rangeley/sata.c
@@ -60,7 +60,7 @@ static void sata_init(struct device *dev)
reg16 = pci_read_config16(dev, PCI_COMMAND);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set the controller mode */
diff --git a/src/southbridge/intel/i3100/lpc.c b/src/southbridge/intel/i3100/lpc.c
index 4d529ca093..77853a8631 100644
--- a/src/southbridge/intel/i3100/lpc.c
+++ b/src/southbridge/intel/i3100/lpc.c
@@ -200,13 +200,13 @@ static void i3100_pirq_init(device_t dev)
/* Get the chip configuration */
config = dev->chip_info;
- if(config->pirq_a_d)
+ if (config->pirq_a_d)
pci_write_config32(dev, 0x60, config->pirq_a_d);
- if(config->pirq_e_h)
+ if (config->pirq_e_h)
pci_write_config32(dev, 0x68, config->pirq_e_h);
- for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 326a9e5a43..f4ab2f654f 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -549,7 +549,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/i82801ex/i82801ex.c b/src/southbridge/intel/i82801ex/i82801ex.c
index fc4164523a..e01832059a 100644
--- a/src/southbridge/intel/i82801ex/i82801ex.c
+++ b/src/southbridge/intel/i82801ex/i82801ex.c
@@ -12,10 +12,10 @@ void i82801ex_enable(device_t dev)
/* See if we are behind the i82801ex pci bridge */
lpc_dev = dev_find_slot(dev->bus->secondary, PCI_DEVFN(0x1f, 0));
- if((dev->path.pci.devfn &0xf8)== 0xf8) {
+ if ((dev->path.pci.devfn &0xf8)== 0xf8) {
index = dev->path.pci.devfn & 7;
}
- else if((dev->path.pci.devfn &0xf8)== 0xe8) {
+ else if ((dev->path.pci.devfn &0xf8)== 0xe8) {
index = (dev->path.pci.devfn & 7) +8;
}
if ((!lpc_dev) || (index >= 16) || ((1<<index)&0x3091)) {
diff --git a/src/southbridge/intel/i82801gx/sata.c b/src/southbridge/intel/i82801gx/sata.c
index 9cb6f39c16..2fcb83d9a7 100644
--- a/src/southbridge/intel/i82801gx/sata.c
+++ b/src/southbridge/intel/i82801gx/sata.c
@@ -118,7 +118,7 @@ static void sata_init(struct device *dev)
/* Restrict ports - 0 and 2 only available */
ports &= 0x5;
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
/* Allow both Legacy and Native mode */
pci_write_config8(dev, 0x09, 0x8f);
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index b12828056c..e76087cf21 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -586,7 +586,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
/* IOTRAP(0) SMIC: currently unused */
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 4f308650a6..5f1a44f5b9 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -409,7 +409,7 @@ static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *st
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index d4fbed4e5c..d11d531777 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -768,7 +768,7 @@ static void southbridge_smi_monitor(void)
}
printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc);
- for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
+ for (i=0; i < 4; i++) if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index ffeb8a2fe8..98cd0bc4b1 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -91,7 +91,7 @@ static void sata_init(struct device *dev)
/* SATA Initialization register */
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
- } else if(config->sata_ahci) {
+ } else if (config->sata_ahci) {
u32 *abar;
printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 00:58:50 +0000