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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-11-18 12:41:16 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-11-20 07:28:37 +0100
commitc36af7b00a9854f626894e51fd28c9df6f1e4e43 (patch)
tree90432ea5c8140d8882eecd5c63bedb1251d8da2b /src/southbridge/intel
parent339064a0bfdaffb82ed407772b86826e98f77103 (diff)
downloadcoreboot-c36af7b00a9854f626894e51fd28c9df6f1e4e43.tar.xz
Replace includes of build.h with version.h
As build.h is an auto-generated file it was necessary to add it as an explicit prerequisite in the Makefiles. When this was forgotten abuild would sometimes fail with following error: fatal error: build.h: No such file or directory Fix this error by compiling version.c into all stages. Change-Id: I342f341077cc7496aed279b00baaa957aa2af0db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/7510 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/fsp_rangeley/Makefile.inc1
-rw-r--r--src/southbridge/intel/fsp_rangeley/early_init.c9
2 files changed, 3 insertions, 7 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/Makefile.inc b/src/southbridge/intel/fsp_rangeley/Makefile.inc
index 995d0dc213..48ac522ddd 100644
--- a/src/southbridge/intel/fsp_rangeley/Makefile.inc
+++ b/src/southbridge/intel/fsp_rangeley/Makefile.inc
@@ -37,7 +37,6 @@ romstage-y += romstage.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
-$(obj)/southbridge/intel/fsp_rangeley/early_init.romstage.o : $(obj)/build.h
ifeq ($(CONFIG_INCLUDE_ME),y)
INTERMEDIATE+=rangeley_add_descriptor
diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c
index bd3d12ccb5..844f4b8492 100644
--- a/src/southbridge/intel/fsp_rangeley/early_init.c
+++ b/src/southbridge/intel/fsp_rangeley/early_init.c
@@ -25,7 +25,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <pc80/mc146818rtc.h>
-#include <build.h>
+#include <version.h>
#include <device/pci_def.h>
#include "pci_devs.h"
#include "soc.h"
@@ -59,11 +59,8 @@ static void reset_rtc(void)
if (rtc_failed) {
printk(BIOS_DEBUG,
- "RTC Failure detected. Resetting Date to %x/%x/%x%x\n",
- COREBOOT_BUILD_MONTH_BCD,
- COREBOOT_BUILD_DAY_BCD,
- 0x20,
- COREBOOT_BUILD_YEAR_BCD);
+ "RTC Failure detected. Resetting Date to %s\n",
+ coreboot_dmi_date);
/* Clear the power failure flag */
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);