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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-19 19:50:51 +0300
committerPatrick Georgi <patrick@georgi-clan.de>2014-06-21 08:04:52 +0200
commitc3ed88636a3533b97cef5bcb445cbe61edbfae7f (patch)
tree12b51d3abb1876d41a8fd1b2bcf899e316b3d511 /src/southbridge/intel
parent49380b87d114cf4c1bd6f0692f43e89e73f662b8 (diff)
downloadcoreboot-c3ed88636a3533b97cef5bcb445cbe61edbfae7f.tar.xz
intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6071 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/elog.c2
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/bd82x6x/me.c5
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c5
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/elog.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/lpc.c2
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/me.c5
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/me_8.x.c5
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c2
-rw-r--r--src/southbridge/intel/ibexpeak/me.c5
-rw-r--r--src/southbridge/intel/lynxpoint/elog.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c4
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c4
-rw-r--r--src/southbridge/intel/lynxpoint/usb_xhci.c4
16 files changed, 17 insertions, 36 deletions
diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c
index 09dfcdbc2c..55fe06f45b 100644
--- a/src/southbridge/intel/bd82x6x/elog.c
+++ b/src/southbridge/intel/bd82x6x/elog.c
@@ -80,7 +80,7 @@ void pch_log_state(void)
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index e052150aba..762989559d 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -431,7 +431,7 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 17be63b349..44c72733dc 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -554,12 +554,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index b12a1e6e73..356d9a5d0a 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -535,12 +535,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/fsp_bd82x6x/elog.c b/src/southbridge/intel/fsp_bd82x6x/elog.c
index 09dfcdbc2c..55fe06f45b 100644
--- a/src/southbridge/intel/fsp_bd82x6x/elog.c
+++ b/src/southbridge/intel/fsp_bd82x6x/elog.c
@@ -80,7 +80,7 @@ void pch_log_state(void)
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index 2633a49836..4351e001a3 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -406,7 +406,7 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c
index c61d12b7c9..2282378997 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me.c
@@ -553,12 +553,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
index 8e9a93a58c..1c2ab34ac5 100644
--- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c
@@ -533,12 +533,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index b9caac6eaa..b20833990a 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -330,7 +330,7 @@ static void i82801gx_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 61a11b30db..e8b9f653fa 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -374,7 +374,7 @@ static void i82801ix_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index dca46014d3..ef9a632dde 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -438,7 +438,7 @@ static void pch_lock_smm(struct device *dev)
u8 reg8;
#endif
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(0xe1, 0xb2); // Enable ACPI mode
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 0e1b5b8920..3130631a77 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -436,12 +436,9 @@ static me_bios_path intel_me_path(device_t dev)
struct me_hfs hfs;
struct me_gmes gmes;
-#if CONFIG_HAVE_ACPI_RESUME
/* S3 wake skips all MKHI messages */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3())
return ME_S3WAKE_BIOS_PATH;
- }
-#endif
pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c
index 9ba3a981d3..a2352b387b 100644
--- a/src/southbridge/intel/lynxpoint/elog.c
+++ b/src/southbridge/intel/lynxpoint/elog.c
@@ -161,7 +161,7 @@ void pch_log_state(void)
/* ACPI Wake */
if (pm1_sts & (1 << 15))
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
- acpi_slp_type == 3 ? 3 : 5);
+ acpi_is_wakeup_s3() ? 3 : 5);
/*
* Wake sources
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 5d1bcdd1c9..6f4063752b 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -499,7 +499,7 @@ static void enable_lp_clock_gating(device_t dev)
static void pch_set_acpi_mode(void)
{
#if CONFIG_HAVE_SMI_HANDLER
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT);
@@ -716,7 +716,7 @@ static void pch_lpc_read_resources(device_t dev)
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
- if (acpi_slp_type != 3 && gnvs)
+ if (!acpi_is_wakeup_s3() && gnvs)
memset(gnvs, 0, sizeof(global_nvs_t));
}
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index cb4e97006d..c8ff913824 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -878,13 +878,11 @@ static struct pci_operations pci_ops = {
static void intel_me_enable(device_t dev)
{
-#if CONFIG_HAVE_ACPI_RESUME
/* Avoid talking to the device in S3 path */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
dev->enabled = 0;
pch_disable_devfn(dev);
}
-#endif
}
static struct device_operations device_ops = {
diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 500b57803a..9978c49ff4 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -394,11 +394,9 @@ static void usb_xhci_init(device_t dev)
reg32 |= (1 << 31);
pci_write_config32(dev, 0x40, reg32);
-#if CONFIG_HAVE_ACPI_RESUME
/* Enable ports that are disabled before returning to OS */
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
usb_xhci_enable_ports_usb3(dev);
-#endif
}
static void usb_xhci_set_subsystem(device_t dev, unsigned vendor,
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 03:46:45 +0000