diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-06-17 08:15:39 +0300 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2021-01-10 11:16:55 +0000 |
| commit | d77b5e9f991dddda5278393cd1336d6659f6f703 (patch) | |
| tree | e9fbaa510d68138f48760cc20af6f7b27859eddc /src/southbridge/intel | |
| parent | 81b8472237a1083f8c0224b10da90fd985f8fa9a (diff) | |
| download | coreboot-d77b5e9f991dddda5278393cd1336d6659f6f703.tar.xz | |
ACPI: Drop redundant ChromeOS setup for GNVS
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/lpc.c | 10 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 11 |
3 files changed, 16 insertions, 11 deletions
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 0a99d80620..a37d298d06 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -647,6 +647,11 @@ size_t gnvs_size_of_array(void) return sizeof(struct global_nvs); } +void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return &gnvs->chromeos; +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); @@ -659,11 +664,6 @@ void southbridge_inject_dsdt(const struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - /* Add it to DSDT. */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32) gnvs); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index c4712baf66..39cae48d10 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -458,6 +458,12 @@ size_t gnvs_size_of_array(void) return sizeof(struct global_nvs); } +/* To build emulation/qemu-q35 with CHROMEOS. */ +void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return 0; +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs = acpi_get_gnvs(); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 1f768c2603..ae718c16a5 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -690,6 +690,11 @@ uint32_t *gnvs_cbmc_ptr(struct global_nvs *gnvs) return &gnvs->cbmc; } +void *gnvs_chromeos_ptr(struct global_nvs *gnvs) +{ + return &gnvs->chromeos; +} + void southbridge_inject_dsdt(const struct device *dev) { struct global_nvs *gnvs; @@ -703,12 +708,6 @@ void southbridge_inject_dsdt(const struct device *dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG(CHROMEOS) - chromeos_init_chromeos_acpi(&(gnvs->chromeos)); -#endif - - - /* Add it to DSDT. */ acpigen_write_scope("\\"); acpigen_write_name_dword("NVSA", (u32)gnvs); |