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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-07-16 09:01:43 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 07:28:57 +0100 |
| commit | d8c7d73283676306e383fde4f42547d0ee3b0209 (patch) | |
| tree | 7549ee2905900ca37db49230acf676487a509620 /src/southbridge/intel | |
| parent | 45df5962c7044713f4631f9483426d9241e36bde (diff) | |
| download | coreboot-d8c7d73283676306e383fde4f42547d0ee3b0209.tar.xz | |
lynxpoint: power management setup tweak
Updated from 161 ref code
Change-Id: I3e07935fec1df21f14d97d165792fe54bf9e474c
Reviewed-on: https://gerrit.chromium.org/gerrit/62128
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4372
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index b6e4e87872..5d1bcdd1c9 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -460,13 +460,12 @@ static void enable_lp_clock_gating(device_t dev) * RCBA + 0x2614[27:25,14:13,10,8] = 101,11,1,1 * RCBA + 0x2614[23:16] = 0x20 * RCBA + 0x2614[30:28] = 0x0 - * RCBA + 0x2614[26] = 1 (IF B2 STEP && 0:31.0@0xFA > 4) + * RCBA + 0x2614[26] = 1 (IF 0:2.0@0x08 >= 0x0b) */ RCBA32_AND_OR(0x2614, 0x8bffffff, 0x0a206500); /* Check for LPT-LP B2 stepping and 0:31.0@0xFA > 4 */ - if (pch_silicon_revision() >= LPT_LP_STEP_B2 && - pci_read_config8(dev, 0xfa) > 4) + if (pci_read_config8(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x8) >= 0x0b) RCBA32_OR(0x2614, (1<<26)); RCBA32_OR(0x900, 0x0000031f); |