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| author | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 13:55:41 +0000 |
|---|---|---|
| committer | Steven J. Magnani <steve@digidescorp.com> | 2005-09-14 13:55:41 +0000 |
| commit | eb065f0620b529573b53ba2bee11dffbd035cdb8 (patch) | |
| tree | 9b6eb0e3a8ba4764adb6f98e5e703d4265c1a116 /src/southbridge/intel | |
| parent | af0cf12eff778207013b4da80738a612f14a3056 (diff) | |
| download | coreboot-eb065f0620b529573b53ba2bee11dffbd035cdb8.tar.xz | |
Add some P64H2-specific definitions, remove some generic PCI ones.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2034 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82870/82870.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index f9289d4027..b869de67b0 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -1,6 +1,4 @@ /* for io apic 1461 */ -#define PCICMD 0x04 -#define SUBSYS 0x2c #define MBAR 0x10 #define ABAR 0x40 @@ -8,3 +6,10 @@ #define MTT 0x042 #define HCCR 0x0f0 #define ACNF 0x0e0 +#define STRP 0x44 // Strap status register + +#define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN) +#define STRP_HPCAP 0x0002 // Hot-plug capable (Hx_SLOT zero/nonzero) + +#define ACNF_SYNCPH 0x0010 // PCI(-X) input clock is synchronous to hub input clock + |