src/southbridge: change "unsigned" to "unsigned int"

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iee2056a50a1201626fa29194afdbfc1f11094420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36333
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

32 files changed, 79 insertions, 79 deletions

diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index d3847a5018..f5700401be 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -51,7 +51,7 @@ void enable_smbus(void)
 	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 1670091055..ea60085624 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -154,7 +154,7 @@ static inline u32 read_cb(void)
 static int mei_wait_for_me_ready(void)
 {
 	struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
 
 	while (try--) {
 		read_me_csr(&me);
@@ -195,7 +195,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
 			void *req_data)
 {
 	struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
 	u32 *data;
 
 	/* Number of dwords to write, ignoring MKHI */
@@ -260,8 +260,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
 	struct mei_header mei_rsp;
 	struct mkhi_header mkhi_rsp;
 	struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
 	u32 *data;
 
 	/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 954353698d..54c3fff05c 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -156,7 +156,7 @@ static inline u32 read_cb(void)
 static int mei_wait_for_me_ready(void)
 {
 	struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
 
 	while (try--) {
 		read_me_csr(&me);
@@ -197,7 +197,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
 			void *req_data)
 {
 	struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
 	u32 *data;
 
 	/* Number of dwords to write, ignoring MKHI */
@@ -262,8 +262,8 @@ static int mei_recv_msg(struct mkhi_header *mkhi,
 	struct mei_header mei_rsp;
 	struct mkhi_header mkhi_rsp;
 	struct mei_csr me, host;
-	unsigned ndata, n/*, me_data_len*/;
-	unsigned expected;
+	unsigned int ndata, n/*, me_data_len*/;
+	unsigned int expected;
 	u32 *data;
 
 	/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 475def33e4..de7fc36ef6 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -87,7 +87,7 @@ int pch_silicon_supported(int type, int rev)
 #define IOBP_RETRY 1000
 static inline int iobp_poll(void)
 {
-	unsigned try = IOBP_RETRY;
+	unsigned int try = IOBP_RETRY;
 	u32 data;
 
 	while (try--) {
@@ -147,7 +147,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
 
 #ifndef __SMM__
 /* Set bit in function disable register to hide this device */
-static void pch_hide_devfn(unsigned devfn)
+static void pch_hide_devfn(unsigned int devfn)
 {
 	switch (devfn) {
 	case PCI_DEVFN(20, 0): /* xHCI */
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 22b91073ce..ac976c2982 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -66,7 +66,7 @@ void enable_smbus(void);
 void enable_usb_bar(void);
 
 #if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 #endif
 
 void early_thermal_init(void);
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index 2c2f9d97e9..98a4bdbe60 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -74,8 +74,8 @@ static void usb_ehci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
 	u8 access_cntl;
 
diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c
index 0245f4fc2d..0669b5fcca 100644
--- a/src/southbridge/intel/common/gpio.c
+++ b/src/southbridge/intel/common/gpio.c
@@ -124,11 +124,11 @@ int get_gpio(int gpio_num)
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
 {
 	int gpio;
-	unsigned bitmask = 1;
-	unsigned vector = 0;
+	unsigned int bitmask = 1;
+	unsigned int vector = 0;
 
 	while (bitmask &&
 	       ((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h
index 019009ef18..eba2d0130f 100644
--- a/src/southbridge/intel/common/gpio.h
+++ b/src/southbridge/intel/common/gpio.h
@@ -172,7 +172,7 @@ int get_gpio(int gpio_num);
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
 
 void set_gpio(int gpio_num, int value);
 
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 73181cfd54..a84a0dfb8f 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -102,7 +102,7 @@ struct ich_spi_controller {
 	uint16_t *optype;
 	uint32_t *addr;
 	uint8_t *data;
-	unsigned databytes;
+	unsigned int databytes;
 	uint8_t *status;
 	uint16_t *control;
 	uint32_t *bbar;
@@ -169,7 +169,7 @@ static u8 readb_(const void *addr)
 	u8 v = read8(addr);
 
 	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -178,7 +178,7 @@ static u16 readw_(const void *addr)
 	u16 v = read16(addr);
 
 	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -187,7 +187,7 @@ static u32 readl_(const void *addr)
 	u32 v = read32(addr);
 
 	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -195,21 +195,21 @@ static void writeb_(u8 b, void *addr)
 {
 	write8(addr, b);
 	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, void *addr)
 {
 	write16(addr, b);
 	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 static void writel_(u32 b, void *addr)
 {
 	write32(addr, b);
 	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
@@ -367,13 +367,13 @@ typedef struct spi_transaction {
 	uint32_t offset;
 } spi_transaction;
 
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 {
 	trans->out += bytes;
 	trans->bytesout -= bytes;
 }
 
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 {
 	trans->in += bytes;
 	trans->bytesin -= bytes;
@@ -801,8 +801,8 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
 	if (addr + len > flash->size) {
 		printk(BIOS_ERR,
 			"Attempt to read %x-%x which is out of chip\n",
-			(unsigned) addr,
-			(unsigned) addr+(unsigned) len);
+			(unsigned int) addr,
+			(unsigned int) addr+(unsigned int) len);
 		return -1;
 	}
 
@@ -872,7 +872,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
 	if (addr + len > flash->size) {
 		printk(BIOS_ERR,
 			"Attempt to write 0x%x-0x%x which is out of chip\n",
-			(unsigned)addr, (unsigned) (addr+len));
+			(unsigned int)addr, (unsigned int) (addr+len));
 		return -1;
 	}
 
@@ -906,7 +906,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
 		len -= block_len;
 	}
 	printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n",
-	       (unsigned) (addr - start), start);
+	       (unsigned int) (addr - start), start);
 	return 0;
 }
 
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index 48b7769925..da0c54be3f 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -51,7 +51,7 @@ void enable_smbus(void)
 	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/fsp_rangeley/gpio.h b/src/southbridge/intel/fsp_rangeley/gpio.h
index 1a916f4dcc..6a27fea861 100644
--- a/src/southbridge/intel/fsp_rangeley/gpio.h
+++ b/src/southbridge/intel/fsp_rangeley/gpio.h
@@ -119,6 +119,6 @@ int get_gpio(int gpio_num);
  * Get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of GPIO pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
 
 #endif
diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c
index ec66c430a9..3512f196d3 100644
--- a/src/southbridge/intel/fsp_rangeley/soc.c
+++ b/src/southbridge/intel/fsp_rangeley/soc.c
@@ -59,7 +59,7 @@ int soc_silicon_supported(int type, int rev)
 }
 
 /* Set bit in Function Disable register to hide this device */
-static void soc_hide_devfn(unsigned devfn)
+static void soc_hide_devfn(unsigned int devfn)
 {
 /* TODO Function Disable. */
 }
diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c
index d2f2a0bd32..f58677ba27 100644
--- a/src/southbridge/intel/fsp_rangeley/spi.c
+++ b/src/southbridge/intel/fsp_rangeley/spi.c
@@ -121,7 +121,7 @@ typedef struct ich_spi_controller {
 	uint16_t *optype;
 	uint32_t *addr;
 	uint8_t *data;
-	unsigned databytes;
+	unsigned int databytes;
 	uint8_t *status;
 	uint16_t *control;
 	uint32_t *bbar;
@@ -199,7 +199,7 @@ static u8 readb_(const void *addr)
 {
 	u8 v = read8(addr);
 	printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -207,7 +207,7 @@ static u16 readw_(const void *addr)
 {
 	u16 v = read16(addr);
 	printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -215,7 +215,7 @@ static u32 readl_(const void *addr)
 {
 	u32 v = read32(addr);
 	printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
-	       v, ((unsigned) addr & 0xffff) - 0xf020);
+	       v, ((unsigned int) addr & 0xffff) - 0xf020);
 	return v;
 }
 
@@ -223,21 +223,21 @@ static void writeb_(u8 b, const void *addr)
 {
 	write8(addr, b);
 	printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 static void writew_(u16 b, const void *addr)
 {
 	write16(addr, b);
 	printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 static void writel_(u32 b, const void *addr)
 {
 	write32((unsigned long)addr, b);
 	printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
-	       b, ((unsigned) addr & 0xffff) - 0xf020);
+	       b, ((unsigned int) addr & 0xffff) - 0xf020);
 }
 
 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
@@ -397,13 +397,13 @@ typedef struct spi_transaction {
 	uint32_t offset;
 } spi_transaction;
 
-static inline void spi_use_out(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 {
 	trans->out += bytes;
 	trans->bytesout -= bytes;
 }
 
-static inline void spi_use_in(spi_transaction *trans, unsigned bytes)
+static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 {
 	trans->in += bytes;
 	trans->bytesin -= bytes;
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index 9aa3017b00..50122d830b 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -36,7 +36,7 @@
 
 void i82801dx_enable(struct device *dev);
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 void aseg_smm_lock(void);
 
 #endif
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 6949a309f6..54ad3c369b 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
 	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c
index 341a98aec4..132b684f30 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.c
+++ b/src/southbridge/intel/i82801ix/i82801ix.c
@@ -137,7 +137,7 @@ static void i82801ix_ehci_init(void)
 					   (1 << 29) | (1 << 17) | (2 << 2));
 }
 
-static int i82801ix_function_disabled(const unsigned devfn)
+static int i82801ix_function_disabled(const unsigned int devfn)
 {
 	struct device *const dev = pcidev_path_on_root(devfn);
 	if (!dev) {
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 7c4faf0142..906d24e95b 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -215,7 +215,7 @@ void i82801ix_dmi_setup(void);
 void i82801ix_dmi_poll_vc1(void);
 
 #if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 #endif
 
 #endif
diff --git a/src/southbridge/intel/i82801ix/usb_ehci.c b/src/southbridge/intel/i82801ix/usb_ehci.c
index f7d8b87828..47254f94b9 100644
--- a/src/southbridge/intel/i82801ix/usb_ehci.c
+++ b/src/southbridge/intel/i82801ix/usb_ehci.c
@@ -34,8 +34,8 @@ static void usb_ehci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
 	u8 access_cntl;
 
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index d2b87d1812..adba27ca71 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -47,7 +47,7 @@ void enable_smbus(void)
 	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index 28c9f68ea2..7b882181ff 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -227,7 +227,7 @@ static inline int lpc_is_mobile(const u16 devid)
 
 #if ENV_ROMSTAGE
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes,
 		u8 *buf);
 int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
diff --git a/src/southbridge/intel/i82801jx/usb_ehci.c b/src/southbridge/intel/i82801jx/usb_ehci.c
index a4f5a01dc1..a24685a26c 100644
--- a/src/southbridge/intel/i82801jx/usb_ehci.c
+++ b/src/southbridge/intel/i82801jx/usb_ehci.c
@@ -34,8 +34,8 @@ static void usb_ehci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
 	u8 access_cntl;
 
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 241584bb49..bd130c0a99 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -51,22 +51,22 @@ void enable_smbus(void)
 	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
-int smbus_write_byte(unsigned device, unsigned address, u8 data)
+int smbus_write_byte(unsigned int device, unsigned int address, u8 data)
 {
   return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data);
 }
 
-int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf)
+int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf)
 {
 	return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf);
 }
 
-int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf)
+int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf)
 {
 	return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf);
 }
diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c
index 8d3ae02179..f804126654 100644
--- a/src/southbridge/intel/ibexpeak/me.c
+++ b/src/southbridge/intel/ibexpeak/me.c
@@ -155,7 +155,7 @@ static inline u32 read_cb(void)
 static int mei_wait_for_me_ready(void)
 {
 	struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
 
 	while (try--) {
 		read_me_csr(&me);
@@ -196,7 +196,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
 			void *req_data)
 {
 	struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
 	u32 *data;
 
 	/* Number of dwords to write, ignoring MKHI */
@@ -261,8 +261,8 @@ static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
 	struct mei_header mei_rsp;
 	struct mkhi_header mkhi_rsp;
 	struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
 	u32 *data;
 
 	/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 9e5fa24e9f..9ee76f22f4 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -56,10 +56,10 @@ void enable_smbus(void);
 void enable_usb_bar(void);
 
 #if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
-int smbus_write_byte(unsigned device, unsigned address, u8 data);
-int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
-int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
+int smbus_read_byte(unsigned int device, unsigned int address);
+int smbus_write_byte(unsigned int device, unsigned int address, u8 data);
+int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);
+int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf);
 #endif
 
 void early_pch_init(void);
diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c
index 95cac8123c..d31fd7028c 100644
--- a/src/southbridge/intel/ibexpeak/usb_ehci.c
+++ b/src/southbridge/intel/ibexpeak/usb_ehci.c
@@ -68,8 +68,8 @@ static void usb_ehci_init(struct device *dev)
 	printk(BIOS_DEBUG, "done.\n");
 }
 
-static void usb_ehci_set_subsystem(struct device *dev, unsigned vendor,
-				   unsigned device)
+static void usb_ehci_set_subsystem(struct device *dev, unsigned int vendor,
+				   unsigned int device)
 {
 	u8 access_cntl;
 
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index d3847a5018..f5700401be 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -51,7 +51,7 @@ void enable_smbus(void)
 	printk(BIOS_DEBUG, "SMBus controller enabled.\n");
 }
 
-int smbus_read_byte(unsigned device, unsigned address)
+int smbus_read_byte(unsigned int device, unsigned int address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index bc8d8a1630..1919d58998 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -127,11 +127,11 @@ int get_gpio(int gpio_num)
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array)
+unsigned int get_gpios(const int *gpio_num_array)
 {
 	int gpio;
-	unsigned bitmask = 1;
-	unsigned vector = 0;
+	unsigned int bitmask = 1;
+	unsigned int vector = 0;
 
 	while (bitmask &&
 	       ((gpio = *gpio_num_array++) != -1)) {
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index fa6d700fd9..8436243f59 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -169,7 +169,7 @@ int get_gpio(int gpio_num);
  * get a number comprised of multiple GPIO values. gpio_num_array points to
  * the array of gpio pin numbers to scan, terminated by -1.
  */
-unsigned get_gpios(const int *gpio_num_array);
+unsigned int get_gpios(const int *gpio_num_array);
 
 void set_gpio(int gpio_num, int value);
 
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index b43a1ae39c..59a8666547 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -162,7 +162,7 @@ static inline u32 read_cb(void)
 static int mei_wait_for_me_ready(void)
 {
 	struct mei_csr me;
-	unsigned try = ME_RETRY;
+	unsigned int try = ME_RETRY;
 
 	while (try--) {
 		read_me_csr(&me);
@@ -202,7 +202,7 @@ static void mei_reset(void)
 static int mei_send_packet(struct mei_header *mei, void *req_data)
 {
 	struct mei_csr host;
-	unsigned ndata, n;
+	unsigned int ndata, n;
 	u32 *data;
 
 	/* Number of dwords to write */
@@ -306,8 +306,8 @@ static int mei_recv_msg(void *header, int header_bytes,
 {
 	struct mei_header mei_rsp;
 	struct mei_csr me, host;
-	unsigned ndata, n;
-	unsigned expected;
+	unsigned int ndata, n;
+	unsigned int expected;
 	u32 *data;
 
 	/* Total number of dwords to read from circular buffer */
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index a57bae311d..dc7b9580d9 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -197,7 +197,7 @@ void pch_disable_devfn(struct device *dev)
 #define IOBP_RETRY 1000
 static inline int iobp_poll(void)
 {
-	unsigned try;
+	unsigned int try;
 
 	for (try = IOBP_RETRY; try > 0; try--) {
 		u16 status = RCBA16(IOBPS);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index be4285b1da..d83dd17275 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -177,7 +177,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
 void enable_smbus(void);
 
 #if ENV_ROMSTAGE
-int smbus_read_byte(unsigned device, unsigned address);
+int smbus_read_byte(unsigned int device, unsigned int address);
 #endif
 
 void enable_usb_bar(void);
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 1eb8e4bcc4..92dd02e2ed 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -168,7 +168,7 @@ static void root_port_init_config(struct device *dev)
 static void pch_pcie_device_set_func(int index, int pci_func)
 {
 	struct device *dev;
-	unsigned new_devfn;
+	unsigned int new_devfn;
 
 	dev = rpc.ports[index];