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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-20 12:24:25 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-25 09:15:44 +0000 |
| commit | 21c9aa125cffbc6458b7c4f442927e372da7aefb (patch) | |
| tree | 96c1c5161203f798e99a5c012621e31a55ae857d /src/southbridge/intel | |
| parent | d64b04609d34e272cb06e9c8f27f4321558e8330 (diff) | |
| download | coreboot-21c9aa125cffbc6458b7c4f442927e372da7aefb.tar.xz | |
sb/intel/i82801ix: Update comment on default decoded IO ranges
Now the comment matches what is programmed into LPC_EN.
Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36995
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 51ce9e859e..92db7d833c 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -76,6 +76,8 @@ void i82801ix_lpc_decode(void) * - 0x378-0x37f and 0x778-0x77f LPT * - 0x2f8-0x2ff COMB * - 0x3f8-0x3ff COMA + * - 0x208-0x20f GAMEH + * - 0x200-0x207 GAMEL */ pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); |