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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-02 14:33:34 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-10-06 10:13:32 +0000 |
| commit | 37e1d93ca0da15c03be32514e45f3668060aac08 (patch) | |
| tree | 5d0bccf93debb19e78496d20a76e408be2871b38 /src/southbridge/intel | |
| parent | d0310faa3bc4d3b62d17d632fbaee98c146eebe0 (diff) | |
| download | coreboot-37e1d93ca0da15c03be32514e45f3668060aac08.tar.xz | |
sb/intel/ibexpeak: Fix enabling HPET
RCBA_HPTC needs to be read back to properly work.
This fixes SeaBIOS endlessly waiting for input instead of booting the
default entry. Linux already fixes this itself.
Change-Id: I22b8b34924f2add2185ec46470c1559bf2fb6d58
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35757
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/ibexpeak/lpc.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index ec9b045f24..e433530bae 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -394,6 +394,7 @@ static void enable_hpet(void) reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; + RCBA32(HPTC); /* Read back for it to work */ write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); } |