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authorStefan Reinauer <stefan.reinauer@coreboot.org>2013-05-07 20:35:29 +0200
committerRonald G. Minnich <rminnich@gmail.com>2013-05-10 00:06:46 +0200
commit3f5f6d8368031710d4f5847ff285812fcde54009 (patch)
tree5031f39d3a5d9e21dc3bc31b56074bbceba4d344 /src/southbridge/intel
parentd654f42e271b2daa17a4daddcb7c9603aa25e018 (diff)
downloadcoreboot-3f5f6d8368031710d4f5847ff285812fcde54009.tar.xz
Drop prototype guarding for romcc
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1] made romcc not choke on function prototypes anymore. This allows us to get rid of a lot of ifdefs guarding __ROMCC__ . [1] http://review.coreboot.org/2424 Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3216 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/pch.h2
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb.h13
-rw-r--r--src/southbridge/intel/i82801ax/i82801ax.h4
-rw-r--r--src/southbridge/intel/i82801bx/i82801bx.h2
-rw-r--r--src/southbridge/intel/i82801dx/i82801dx.h2
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h2
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h3
7 files changed, 9 insertions, 19 deletions
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7f64571c4b..39048662db 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -56,7 +56,7 @@
void intel_pch_finalize_smm(void);
#endif
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
#if !defined(__SMM__)
#include "chip.h"
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 76d5fc7085..e6062c68e8 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -21,26 +21,19 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#if !defined(__ASSEMBLER__)
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
#if !defined(__PRE_RAM__)
-#if !defined(__ACPI__) /* dsdt include */
-
#include <arch/io.h>
#include <device/device.h>
#include "chip.h"
-
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);
-
-#endif
-#endif
-#endif
-
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#else
void enable_smbus(void);
int smbus_read_byte(u8 device, u8 address);
void enable_pm(void);
#endif
+#endif
/* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the
* 'reg' variable, otherwise it clears those bits.
diff --git a/src/southbridge/intel/i82801ax/i82801ax.h b/src/southbridge/intel/i82801ax/i82801ax.h
index ed15bba5fd..f459f2f20a 100644
--- a/src/southbridge/intel/i82801ax/i82801ax.h
+++ b/src/southbridge/intel/i82801ax/i82801ax.h
@@ -24,9 +24,7 @@
#if !defined(__PRE_RAM__)
#include "chip.h"
void i82801ax_enable(device_t dev);
-#endif
-
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#else
void enable_smbus(void);
int smbus_read_byte(u8 device, u8 address);
#endif
diff --git a/src/southbridge/intel/i82801bx/i82801bx.h b/src/southbridge/intel/i82801bx/i82801bx.h
index 202b41cbff..b2ee79c745 100644
--- a/src/southbridge/intel/i82801bx/i82801bx.h
+++ b/src/southbridge/intel/i82801bx/i82801bx.h
@@ -26,7 +26,7 @@
extern void i82801bx_enable(device_t dev);
#endif
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
+#if defined(__PRE_RAM__)
void enable_smbus(void);
int smbus_read_byte(u8 device, u8 address);
#endif
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index dba5bd6d8d..c7d7e77e79 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -31,7 +31,7 @@
#ifndef I82801DX_H
#define I82801DX_H
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801dx_enable(device_t dev);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index b5df5d9d32..1064dde8a0 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -37,7 +37,7 @@
#ifndef __ACPI__
#define DEBUG_PERIODIC_SMIS 0
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
#if !defined(__PRE_RAM__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 7246739bb5..21933b4660 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -21,7 +21,6 @@
#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
#define SOUTHBRIDGE_INTEL_LYNXPOINT_PCH_H
-
/*
* Lynx Point PCH PCI Devices:
*
@@ -125,7 +124,7 @@ struct rcba_config_instruction
u32 or_value;
};
-#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__)
void pch_config_rcba(const struct rcba_config_instruction *rcba_config);
int pch_silicon_revision(void);
int pch_silicon_type(void);