summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorPaul Menzel <paulepanter@users.sourceforge.net>2013-04-23 13:00:34 +0200
committerRonald G. Minnich <rminnich@gmail.com>2013-04-26 18:37:00 +0200
commit526a46ed7e4feb9e2cb02dffccbf40182c8cc014 (patch)
tree215e7cc41245240b806abff1315d017c28e723df /src/southbridge/intel
parentdfad17de0293a56f68626ce47bfc14300f15e15c (diff)
downloadcoreboot-526a46ed7e4feb9e2cb02dffccbf40182c8cc014.tar.xz
Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2
Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 3a94e84062..777a6d772f 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -52,12 +52,12 @@ static void i82801gx_enable_apic(struct device *dev)
pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
*ioapic_index = 0;
- *ioapic_data = (1 << 25);
+ *ioapic_data = (2 << 24);
*ioapic_index = 0;
reg32 = *ioapic_data;
printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
- if (reg32 != (1 << 25))
+ if (reg32 != (2 << 24))
die("APIC Error\n");
printk(BIOS_SPEW, "Dumping IOAPIC registers\n");