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authorKyösti Mälkki <kyosti.malkki@gmail.com>2013-06-19 23:05:00 +0300
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 01:24:42 +0200
commit54d6abd276ac5c60e3846266050167cc1754dcf0 (patch)
treedecf02bd60f82990b39cae0b93da4e198ab36d63 /src/southbridge/intel
parent872c9222965909dffdd091e644b03e676ca2754f (diff)
downloadcoreboot-54d6abd276ac5c60e3846266050167cc1754dcf0.tar.xz
Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to combine these with MMCONF_SUPPORT in arch/io.h. Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3502 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/finalize.c1
-rw-r--r--src/southbridge/intel/bd82x6x/me.c2
-rw-r--r--src/southbridge/intel/bd82x6x/me_8.x.c2
-rw-r--r--src/southbridge/intel/bd82x6x/smihandler.c2
-rw-r--r--src/southbridge/intel/bd82x6x/spi.c2
-rw-r--r--src/southbridge/intel/i82801dx/smihandler.c6
-rw-r--r--src/southbridge/intel/i82801gx/smihandler.c2
-rw-r--r--src/southbridge/intel/sch/smihandler.c7
8 files changed, 5 insertions, 19 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index 331e26cab1..76e75c8240 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,7 +20,6 @@
#include <arch/io.h>
#include <console/post_codes.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
#include "pch.h"
#include <spi-generic.h>
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index 7fdf9261f8..626e61a96a 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -38,7 +38,7 @@
#include <elog.h>
#ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
#else
# include <device/device.h>
# include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index f79adf59c0..72175d81a3 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -38,7 +38,7 @@
#include <elog.h>
#ifdef __SMM__
-# include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
#else
# include <device/device.h>
# include <device/pci.h>
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 591311555d..9588703c6d 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -37,7 +37,7 @@
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 09169b1bc8..c720afeed5 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -34,7 +34,7 @@
#define min(a, b) ((a)<(b)?(a):(b))
#ifdef __SMM__
-#include <northbridge/intel/sandybridge/pcie_config.c>
+#include <arch/pci_mmio_cfg.h>
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pcie_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index 5470890d26..9b0c235d97 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -207,12 +207,6 @@ static void dump_tco_status(u32 tco_sts)
printk(BIOS_DEBUG, "\n");
}
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-// #include "../../../northbridge/intel/i945/pcie_config.c"
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index d143ce393a..03c5d0912c 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -207,7 +207,7 @@ static void dump_tco_status(u32 tco_sts)
* 1. the chipset can do it
* 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
*/
-#include "../../../northbridge/intel/i945/pcie_config.c"
+#include <arch/pci_mmio_cfg.h>
int southbridge_io_trap_handler(int smif)
{
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c
index 2ccbc7f9ba..507413820a 100644
--- a/src/southbridge/intel/sch/smihandler.c
+++ b/src/southbridge/intel/sch/smihandler.c
@@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts)
}
#endif
-
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-//#include "../../../northbridge/intel/i945/pcie_config.c"
-
int southbridge_io_trap_handler(int smif)
{
//global_nvs_t *gnvs = (global_nvs_t *)0xc00;