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authorJoseph Smith <joe@settoplinux.org>2009-05-29 13:45:22 +0000
committerJoseph Smith <joe@smittys.pointclark.net>2009-05-29 13:45:22 +0000
commit60f0f1b18f87332a569ced6c8744a1572517ba39 (patch)
tree8a278fad3d544363b676e11800e38365a71b2b11 /src/southbridge/intel
parentf8a5c6ec02f1e21d62756bda07f755b3a2f4865f (diff)
downloadcoreboot-60f0f1b18f87332a569ced6c8744a1572517ba39.tar.xz
enable/disable IDE 0/1 (Primary/Secondary) interfaces on the i82801xx southbridge.
Signed-off-by: Joseph Smith <joe@settoplinux.org> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801xx/chip.h2
-rw-r--r--src/southbridge/intel/i82801xx/i82801xx_ide.c19
2 files changed, 15 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801xx/chip.h b/src/southbridge/intel/i82801xx/chip.h
index d86c07e8e0..d159aa2be0 100644
--- a/src/southbridge/intel/i82801xx/chip.h
+++ b/src/southbridge/intel/i82801xx/chip.h
@@ -43,6 +43,8 @@ struct southbridge_intel_i82801xx_config {
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
+ uint8_t ide0_enable;
+ uint8_t ide1_enable;
};
extern struct chip_operations southbridge_intel_i82801xx_ops;
diff --git a/src/southbridge/intel/i82801xx/i82801xx_ide.c b/src/southbridge/intel/i82801xx/i82801xx_ide.c
index f9ba3903e3..4173cc6a75 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_ide.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_ide.c
@@ -27,29 +27,36 @@
#include <device/pci_ids.h>
#include "i82801xx.h"
+typedef struct southbridge_intel_i82801xx_config config_t;
+
static void ide_init(struct device *dev)
{
+ /* Get the chip configuration */
+ config_t *config = dev->chip_info;
+
/* TODO: Needs to be tested for compatibility with ICH5(R). */
/* Enable IDE devices so the Linux IDE driver will work. */
uint16_t ideTimingConfig;
- int enable_primary = 1;
- int enable_secondary = 1;
ideTimingConfig = pci_read_config16(dev, IDE_TIM_PRI);
ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (enable_primary) {
+ if (!config || config->ide0_enable) {
/* Enable primary IDE interface. */
ideTimingConfig |= IDE_DECODE_ENABLE;
- printk_debug("IDE0 ");
+ printk_debug("IDE0: Primary IDE interface is enabled\n");
+ } else {
+ printk_info("IDE0: Primary IDE interface is disabled\n");
}
pci_write_config16(dev, IDE_TIM_PRI, ideTimingConfig);
ideTimingConfig = pci_read_config16(dev, IDE_TIM_SEC);
ideTimingConfig &= ~IDE_DECODE_ENABLE;
- if (enable_secondary) {
+ if (!config || config->ide1_enable) {
/* Enable secondary IDE interface. */
ideTimingConfig |= IDE_DECODE_ENABLE;
- printk_debug("IDE1 ");
+ printk_debug("IDE1: Secondary IDE interface is enabled\n");
+ } else {
+ printk_info("IDE1: Secondary IDE interface is disabled\n");
}
pci_write_config16(dev, IDE_TIM_SEC, ideTimingConfig);
}