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authorVladimir Serbinenko <phcoder@gmail.com>2014-08-12 21:40:32 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-08-12 22:37:35 +0200
commitb1f34ab8d53e74c178492d9b001d1f5ef696e884 (patch)
tree7119fe46c5cc956bfa38a6352c0748d25dec2453 /src/southbridge/intel
parent9907be4bbd7f40f5d7466969c8c735b9a84807aa (diff)
downloadcoreboot-b1f34ab8d53e74c178492d9b001d1f5ef696e884.tar.xz
i82801ix: Make RP04 optionally hotpluggable.
Change-Id: I34a1ae4bff22db6ee55fa511de39bdfd5dd92c7e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801ix/acpi/pcie.asl23
-rw-r--r--src/southbridge/intel/i82801ix/acpi/pcie_port.asl36
2 files changed, 53 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801ix/acpi/pcie.asl b/src/southbridge/intel/i82801ix/acpi/pcie.asl
index 89d2485660..f02ad021c6 100644
--- a/src/southbridge/intel/i82801ix/acpi/pcie.asl
+++ b/src/southbridge/intel/i82801ix/acpi/pcie.asl
@@ -26,7 +26,7 @@
Device (RP01)
{
NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //#include "pcie_port.asl"
+#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -52,7 +52,7 @@ Device (RP01)
Device (RP02)
{
NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //#include "pcie_port.asl"
+#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -79,7 +79,7 @@ Device (RP02)
Device (RP03)
{
NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //#include "pcie_port.asl"
+#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -106,7 +106,7 @@ Device (RP03)
Device (RP04)
{
NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //#include "pcie_port.asl"
+#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -127,13 +127,24 @@ Device (RP04)
}
}
+
+#ifdef RP04_IS_EXPRESSCARD
+ Device (SLOT)
+ {
+ Name (_ADR, 0x00)
+ Method (_RMV, 0, NotSerialized)
+ {
+ Return (0x01)
+ }
+ }
+#endif
}
Device (RP05)
{
NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //#include "pcie_port.asl"
+#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
@@ -160,7 +171,7 @@ Device (RP05)
Device (RP06)
{
NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
- //#include "pcie_port.asl"
+#include "pcie_port.asl"
Method(_PRT)
{
If (PICM) {
diff --git a/src/southbridge/intel/i82801ix/acpi/pcie_port.asl b/src/southbridge/intel/i82801ix/acpi/pcie_port.asl
new file mode 100644
index 0000000000..7c50bd64ae
--- /dev/null
+++ b/src/southbridge/intel/i82801ix/acpi/pcie_port.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Included in each PCIe Root Port device */
+
+OperationRegion (RPCS, PCI_Config, 0x00, 0xFF)
+Field (RPCS, AnyAcc, NoLock, Preserve)
+{
+ Offset (0x4c), // Link Capabilities
+ , 24,
+ RPPN, 8, // Root Port Number
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1,
+}