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authorMatt DeVillier <matt.devillier@gmail.com>2020-03-30 20:05:49 -0500
committerMatt DeVillier <matt.devillier@gmail.com>2020-04-02 20:31:24 +0000
commitc821f00b518c82d20672be844c3a3ef4807112fe (patch)
tree2c0ec3c19beb2dec88fcdb679a3757891a40dbaa /src/southbridge/intel
parent948a5d0310f6a4f7b34cd416b81d0e56fd3ce3d4 (diff)
downloadcoreboot-c821f00b518c82d20672be844c3a3ef4807112fe.tar.xz
sb/intel/bd82x6x: drop IGD-related NVS variables
NDID/DID entries are no longer used by the GMA SSDT generator, so drop them. SSDT generation will be simplified in a subsequent commit. Change-Id: Ie7491409681d8c2721dd6d6a16a8d5004cd0cf8a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/globalnvs.asl7
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c7
-rw-r--r--src/southbridge/intel/bd82x6x/nvs.h5
3 files changed, 1 insertions, 18 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index 1b23cef6ac..ac42c7a327 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -88,13 +88,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TLST, 8, // 0x3d - Display Toggle List pointer
CADL, 8, // 0x3e - Currently Attached Devices List
PADL, 8, // 0x3f - Previously Attached Devices List
- Offset (0x46),
- NDID, 8, // 0x46 - Number of Device IDs
- DID1, 32, // 0x47 - Device ID 1
- DID2, 32, // 0x4b - Device ID 2
- DID3, 32, // 0x4f - Device ID 3
- DID4, 32, // 0x53 - Device ID 4
- DID5, 32, // 0x57 - Device ID 5
/* Backlight Control */
Offset (0x64),
BLCS, 8, // 0x64 - Backlight control possible?
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 1f921936d9..91d710e2a0 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -26,7 +26,6 @@
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
-#include <drivers/intel/gma/i915.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <string.h>
@@ -673,7 +672,6 @@ static void southbridge_inject_dsdt(struct device *dev)
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
- const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
@@ -682,11 +680,6 @@ static void southbridge_inject_dsdt(struct device *dev)
gnvs->mpen = 1; /* Enable Multi Processing */
gnvs->pcnt = dev_count_cpu();
- if (gfx) {
- gnvs->ndid = gfx->ndid;
- memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
- }
-
#if CONFIG(CHROMEOS)
chromeos_init_chromeos_acpi(&(gnvs->chromeos));
#endif
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 93ebed66ec..08b5ebd8ed 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -75,10 +75,7 @@ typedef struct global_nvs_t {
u8 tlst; /* 0x3d - Display Toggle List Pointer */
u8 cadl; /* 0x3e - currently attached devices */
u8 padl; /* 0x3f - previously attached devices */
- u16 rsvd14[3];
- u8 ndid; /* 0x46 - number of device ids */
- u32 did[5]; /* 0x47 - 5b device id 1..5 */
- u8 rsvd5[0x9];
+ u8 rsvd5[36];
/* Backlight Control */
u8 blcs; /* 0x64 - Backlight Control possible */
u8 brtl;