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authorPatrick Rudolph <siro@das-labor.org>2017-04-12 16:50:26 +0200
committerMartin Roth <martinroth@google.com>2017-05-01 16:21:56 +0200
commitd0eb6cd8bd89ee47a8e3bf2948a2ff4196c761e3 (patch)
tree5f1de7b5a284833b07d659be198af5130b2934a3 /src/southbridge/intel
parent0a4a4f7ae4188bccf4147196f08620453ef0633c (diff)
downloadcoreboot-d0eb6cd8bd89ee47a8e3bf2948a2ff4196c761e3.tar.xz
nb/intel/fsp_sandybridge/gma: Set up OpRegion in nb code
Set up IGD OpRegion in northbridge and fill in GNVS' aslb. At this point GNVS already has been set up by SSDT injection. Required for future VBT patches that will: * Use ACPI memory instead of CBMEM * Use common implementation to locate VBT * Fill in platform specific values Change-Id: Ie5d93117ee8bd8d15085aedbfa7358dfcf5f0045 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19307 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/fsp_bd82x6x/lpc.c6
-rw-r--r--src/southbridge/intel/fsp_i89xx/lpc.c6
2 files changed, 0 insertions, 12 deletions
diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c
index c2dea6bca3..963359f873 100644
--- a/src/southbridge/intel/fsp_bd82x6x/lpc.c
+++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c
@@ -589,10 +589,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -600,8 +596,6 @@ static void southbridge_inject_dsdt(device_t dev)
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));
diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c
index 7ebe6e4a11..5ba296956c 100644
--- a/src/southbridge/intel/fsp_i89xx/lpc.c
+++ b/src/southbridge/intel/fsp_i89xx/lpc.c
@@ -501,10 +501,6 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev)
{
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
- void *opregion;
-
- /* Calling northbridge code as gnvs contains opregion address. */
- opregion = igd_make_opregion();
if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
@@ -512,8 +508,6 @@ static void southbridge_inject_dsdt(device_t dev)
memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs);
- /* IGD OpRegion Base Address */
- gnvs->aslb = (u32)opregion;
gnvs->ndid = gfx->ndid;
memcpy(gnvs->did, gfx->did, sizeof(gnvs->did));