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| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-04-12 13:52:12 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-25 15:15:41 +0000 |
| commit | e5c8077c94813fd5003cc62a246f9d2f35f717fc (patch) | |
| tree | 884ec29a42eeb2273050e7f30703487bcbbb3bde /src/southbridge/intel | |
| parent | 87af36ac172b0ec48b078453ed4f2fd8d2a62a22 (diff) | |
| download | coreboot-e5c8077c94813fd5003cc62a246f9d2f35f717fc.tar.xz | |
sb/intel/i82801jx: Add Interrupt pin and routing RCBA offsets macros
Change-Id: If8e82a291f666d5f310422b100f02d5df17ab74e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 9dddd2e922..be92a8b58e 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -188,6 +188,23 @@ #define RCBA_FDSW 0x3420 #define RCBA_MAP 0x35f0 /* UHCI controller #6 remapping */ +#define D31IP 0x3100 /* 32bit */ +#define D30IP 0x3104 /* 32bit R0: does not generate interrupt */ +#define D29IP 0x3108 /* 32bit */ +#define D28IP 0x310c /* 32bit */ +#define D27IP 0x3110 /* 32bit */ +#define D26IP 0x3114 /* 32bit */ +#define D25IP 0x3114 /* 32bit */ + +#define D31IR 0x3140 /* 16bit */ +#define D30IR 0x3142 /* 16bit R0: does not generate interrupt */ +#define D29IR 0x3144 /* 16bit */ +#define D28IR 0x3146 /* 16bit */ +#define D27IR 0x3148 /* 16bit */ +#define D26IR 0x314c /* 16bit */ +#define D25IR 0x3150 /* 16bit */ +#define OIC 0x31ff /* 8bit */ + #define BUC_LAND (1 << 5) /* LAN */ #define FD_SAD2 (1 << 25) /* SATA #2 */ #define FD_TTD (1 << 24) /* Thermal Throttle */ |