diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 13:25:13 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-14 22:26:46 +0000 |
| commit | 07e77f13d4987a4424be254f439bb6ac505761a7 (patch) | |
| tree | 114e5fd1ad8107a2437022b9e83746ef970cc3ee /src/southbridge/intel | |
| parent | 6f7e8dee588de6f425c27a8271e2cdcb8075deeb (diff) | |
| download | coreboot-07e77f13d4987a4424be254f439bb6ac505761a7.tar.xz | |
sb/intel/i82371eb: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Ie366a49045940747eb5cc1e38316cce31c5774cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82371eb/acpi_tables.c | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/fadt.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/i82371eb.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82371eb/isa.c | 4 |
4 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index 59d5dea104..9a720e2cf4 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -26,7 +26,7 @@ static int determine_total_number_of_cores(void) { - device_t cpu; + struct device *cpu; int count = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || @@ -41,7 +41,7 @@ static int determine_total_number_of_cores(void) return count; } -void generate_cpu_entries(device_t device) +void generate_cpu_entries(struct device *device) { int cpu, pcontrol_blk=DEFAULT_PMBASE+PCNTRL, plen=6; int numcpus = determine_total_number_of_cores(); diff --git a/src/southbridge/intel/i82371eb/fadt.c b/src/southbridge/intel/i82371eb/fadt.c index b77ed4a292..41ad31c651 100644 --- a/src/southbridge/intel/i82371eb/fadt.c +++ b/src/southbridge/intel/i82371eb/fadt.c @@ -31,7 +31,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - device_t dev; + struct device *dev; /* Power management controller */ dev = dev_find_device(PCI_VENDOR_ID_INTEL, diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 6908b4558f..1fea0ff46f 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -23,7 +23,7 @@ #include <device/device.h> #include "chip.h" -void i82371eb_enable(device_t dev); +void i82371eb_enable(struct device *dev); void i82371eb_hard_reset(void); #else void enable_smbus(void); diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index 2bab05cb15..8030a750c8 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -36,7 +36,7 @@ static void enable_intel_82093aa_ioapic(void) u8 ioapic_id = 2; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); - device_t dev; + struct device *dev; dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_ISA, 0); @@ -125,7 +125,7 @@ static void sb_read_resources(struct device *dev) } #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -static void southbridge_acpi_fill_ssdt_generator(device_t device) +static void southbridge_acpi_fill_ssdt_generator(struct device *device) { acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); generate_cpu_entries(device); |