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| author | Zheng Bao <zheng.bao@amd.com> | 2009-06-05 10:00:07 +0000 |
|---|---|---|
| committer | Zheng Bao <Zheng.Bao@amd.com> | 2009-06-05 10:00:07 +0000 |
| commit | 28d71b9445ef2774baa5e1f5ad17160d90b0e8bb (patch) | |
| tree | fb70299dea5d7924fe7d63af399e095881511cf9 /src/southbridge/intel | |
| parent | a24e1dd6dacc4036466f5fc8acd5a1c4306790d2 (diff) | |
| download | coreboot-28d71b9445ef2774baa5e1f5ad17160d90b0e8bb.tar.xz | |
After I modify the pci_ext_read_config32 and pci_ext_read_config32, the step 6a
starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.
Tested on dbm690t.
Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.
http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions